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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE REVISION 2.02
3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com
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LIFE SUPPORT POLICY
Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
2)
All other trademarks are of their respective companies.
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REVISION HISTORY
Date
03/26/03 05/14/03
Revision Number
1.00 1.01
Description
First Release of Data Sheet Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device
06/10/03
1.02 Revised temperature support to industrial temperature Revised temperature support back to extended commercial range (0C to 85C)
06/25/03
1.03 Corrected pin descriptions for S_M66EN, P_M66EN, and S_CLKOUT. Corrected MS0 and MS1 pin assignments on Table 2.4. MS0 should be B14 and MS1 should be R16.
07/31/03
1.031
Added PBGA pin assignments to signal descriptions in Section 2.2. Revised power consumption specifications in section 17.6 Revised TDELAY specifications in sections 17.4 and 17.5 Modified spacing on a few chapters. No changes to content. Corrected VDD and VSS pin assignments on Table 2.2.7. Removed pins 106 and 155 (R16 and B14) as these should be MS1 and MS0 respectively. Added Industrial temp and Pb-free parts in the Ordering Information Added Ambient Temperature spec for PI7C8150BI Added industrial temp and Pb-free descriptions to the features section in the introduction Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits[3:2] offset 48h - Extended Chip Control Register (section 14.1.31) Corrected configuration register offset 80h (bit[15:0] is secondary bus master timeout counter and bit[31:16] is primary bus master timeout counter) Revised and added further descriptions for bit[15:0] offset 80h and bit[31:16] offset 80h Corrected Note 4 to show REQ_L has a setup time of 12ns and GNT_L has a setup time of 10ns (section 17.3) Removed `Advance Information' title from headers Removed email (solutions@pericom.com) link Revised PCI Local Bus specification compliance to 2.3
10/20/03 02/13/04 05/20/04 07/06/04
1.04 1.05 1.06 1.061
08/12/04
1.07
09/23/04
2.00
01/10/05
2.01
04/05/06
2.02
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TABLE OF CONTENTS
1 2 INTRODUCTION .............................................................................................................................. 11 SIGNAL DEFINITIONS ................................................................................................................... 12 2.1 SIGNAL TYPES............................................................................................................................... 12 2.2 SIGNALS ........................................................................................................................................ 12 2.2.1 PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12 2.2.3 CLOCK SIGNALS ............................................................................................................... 15 2.2.4 MISCELLANEOUS SIGNALS........................................................................................... 16 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS ........................................................ 17 2.2.6 JTAG BOUNDARY SCAN SIGNALS ................................................................................ 17 2.2.7 POWER AND GROUND..................................................................................................... 18 2.3 PIN LIST - 208-PIN FQFP .......................................................................................................... 18 2.4 PIN LIST - 256-BALL PBGA ..................................................................................................... 20 3 PCI BUS OPERATION ..................................................................................................................... 22 3.1 TYPES OF TRANSACTIONS..................................................................................................... 22 3.2 SINGLE ADDRESS PHASE ....................................................................................................... 23 3.3 DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23 3.4 DATA PHASE ............................................................................................................................. 23 3.5 WRITE TRANSACTIONS .......................................................................................................... 23 3.5.1 MEMORY WRITE TRANSACTIONS................................................................................ 24 3.5.2 MEMORY WRITE AND INVALIDATE ............................................................................ 25 3.5.3 DELAYED WRITE TRANSACTIONS............................................................................... 25 3.5.4 WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 26 3.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 26 3.5.6 FAST BACK-TO-BACK TRANSACTIONS ....................................................................... 27 3.6 READ TRANSACTIONS............................................................................................................ 27 3.6.1 PREFETCHABLE READ TRANSACTIONS.................................................................... 27 3.6.2 NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 27 3.6.3 READ PREFETCH ADDRESS BOUNDARIES ............................................................... 28 3.6.4 DELAYED READ REQUESTS .......................................................................................... 28 3.6.5 DELAYED READ COMPLETION WITH TARGET ........................................................ 29 3.6.6 DELAYED READ COMPLETION ON INITIATOR BUS................................................ 29 3.6.7 FAST BACK-TO-BACK READ TRANSACTION ............................................................. 30 3.7 CONFIGURATION TRANSACTIONS ...................................................................................... 30 3.7.1 TYPE 0 ACCESS TO PI7C8150B....................................................................................... 31 3.7.2 TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 31 3.7.3 TYPE 1 TO TYPE 1 FORWARDING................................................................................. 33 3.7.4 SPECIAL CYCLES ............................................................................................................. 33 3.8 TRANSACTION TERMINATION ............................................................................................. 34 3.8.1 MASTER TERMINATION INITIATED BY PI7C8150B ................................................. 35 3.8.2 MASTER ABORT RECEIVED BY PI7C8150B ................................................................ 36 3.8.3 TARGET TERMINATION RECEIVED BY PI7C8150B.................................................. 36 3.8.4 TARGET TERMINATION INITIATED BY PI7C8150B.................................................. 38 4 ADDRESS DECODING..................................................................................................................... 40 4.1 ADDRESS RANGES ................................................................................................................... 40 4.2 I/O ADDRESS DECODING........................................................................................................ 40 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 41 4.2.2 ISA MODE........................................................................................................................... 42
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4.3 MEMORY ADDRESS DECODING ........................................................................................... 42 4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 43 4.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 44 4.4 VGA SUPPORT........................................................................................................................... 45 4.4.1 VGA MODE......................................................................................................................... 45 4.4.2 VGA SNOOP MODE........................................................................................................... 45 5 TRANSACTION ORDERING.......................................................................................................... 46 5.1 5.2 5.3 5.4 6 TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 46 GENERAL ORDERING GUIDELINES ..................................................................................... 47 ORDERING RULES.................................................................................................................... 48 DATA SYNCHRONIZATION .................................................................................................... 49
ERROR HANDLING......................................................................................................................... 49 6.1 ADDRESS PARITY ERRORS .................................................................................................... 49 6.2 DATA PARITY ERRORS ........................................................................................................... 50 6.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 50 6.2.2 READ TRANSACTIONS .................................................................................................... 51 6.2.3 DELAYED WRITE TRANSACTIONS............................................................................... 52 6.2.4 POSTED WRITE TRANSACTIONS.................................................................................. 54 6.3 DATA PARITY ERROR REPORTING SUMMARY................................................................. 55 6.4 SYSTEM ERROR (SERR_L) REPORTING............................................................................... 59
7
EXCLUSIVE ACCESS ...................................................................................................................... 60 7.1 CONCURRENT LOCKS ............................................................................................................. 60 7.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B .................................................... 60 7.2.1 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 60 7.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 62 7.3 ENDING EXCLUSIVE ACCESS................................................................................................ 62
8
PCI BUS ARBITRATION................................................................................................................. 63 8.1 PRIMARY PCI BUS ARBITRATION ........................................................................................ 63 8.2 SECONDARY PCI BUS ARBITRATION.................................................................................. 63 8.2.1 SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 63 8.2.2 PREEMPTION .................................................................................................................... 65 8.2.3 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 65 8.2.4 BUS PARKING.................................................................................................................... 65
9
CLOCKS ............................................................................................................................................. 66 9.1 9.2 9.3 PRIMARY CLOCK INPUTS....................................................................................................... 66 SECONDARY CLOCK OUTPUTS ............................................................................................ 66 ASYNCHRONOUS MODE......................................................................................................... 66 GENERAL PURPOSE I/O INTERFACE.................................................................................... 67 GPIO CONTROL REGISTERS................................................................................................... 67 SECONDARY CLOCK CONTROL ........................................................................................... 68 LIVE INSERTION ....................................................................................................................... 69 PCI POWER MANAGEMENT .................................................................................................... 70 RESET............................................................................................................................................. 70 PRIMARY INTERFACE RESET................................................................................................ 70 SECONDARY INTERFACE RESET.......................................................................................... 71 CHIP RESET................................................................................................................................ 71
10 10.1 10.2 10.3 11 12 12.1 12.2 12.3
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13 13.1 13.2 14
SUPPORTED COMMANDS......................................................................................................... 72 PRIMARY INTERFACE ............................................................................................................. 72 SECONDARY INTERFACE....................................................................................................... 73 CONFIGURATION REGISTERS................................................................................................ 74
14.1 CONFIGURATION REGISTER ................................................................................................. 74 14.1.1 VENDOR ID REGISTER - OFFSET 00h......................................................................... 75 14.1.2 DEVICE ID REGISTER - OFFSET 00h .......................................................................... 75 14.1.3 COMMAND REGISTER - OFFSET 04h.......................................................................... 75 14.1.4 STATUS REGISTER - OFFSET 04h ................................................................................ 76 14.1.5 REVISION ID REGISTER - OFFSET 08h ...................................................................... 77 14.1.6 CLASS CODE REGISTER - OFFSET 08h....................................................................... 77 14.1.7 CACHE LINE SIZE REGISTER - OFFSET 0Ch ............................................................ 77 14.1.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch ........................................... 77 14.1.9 HEADER TYPE REGISTER - OFFSET 0Ch................................................................... 77 14.1.10 PRIMARY BUS NUMBER REGISTSER - OFFSET 18h............................................ 78 14.1.11 SECONDARY BUS NUMBER REGISTER - OFFSET 18h ........................................ 78 14.1.12 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h.................................... 78 14.1.13 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h .................................. 78 14.1.14 I/O BASE REGISTER - OFFSET 1Ch.......................................................................... 78 14.1.15 I/O LIMIT REGISTER - OFFSET 1Ch ........................................................................ 79 14.1.16 SECONDARY STATUS REGISTER - OFFSET 1Ch................................................... 79 14.1.17 MEMORY BASE REGISTER - OFFSET 20h .............................................................. 80 14.1.18 MEMORY LIMIT REGISTER - OFFSET 20h............................................................. 80 14.1.19 PEFETCHABLE MEMORY BASE REGISTER - OFFSET 24h ................................ 80 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h ............................ 80 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h ....................................................................................................................................... 81 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch....................................................................................................................................... 81 14.1.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h .......................... 81 14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h......................... 81 14.1.25 ECP POINTER REGISTER - OFFSET 34h................................................................. 81 14.1.26 INTERRUPT LINE REGISTER - OFFSET 3Ch ......................................................... 81 14.1.27 INTERRUPT PIN REGISTER - OFFSET 3Ch............................................................ 82 14.1.28 BRIDGE CONTROL REGISTER - OFFSET 3Ch ....................................................... 82 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER - OFFSET 40h.................................. 83 14.1.30 ARBITER CONTROL REGISTER - OFFSET 40h...................................................... 84 14.1.31 EXTENDED CHIP CONTROL REGISTER - OFFSET 48h....................................... 85 14.1.32 UPSTREAM MEMORY CONTROL REGISTER - OFFSET 48h ............................... 85 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER - OFFSET 4Ch .......................................................................................................................................... 86 14.1.34 UPSTREAM (S TO P) MEMORY BASE REGISTER - OFFSET 50h ........................ 86 14.1.35 UPSTREAM (S TO P) MEMORY LIMIT REGISTER - OFFSET 50h....................... 86 14.1.36 UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER - OFFSET 54h .......................................................................................................................................... 87 14.1.37 UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER - OFFSET 58h .......................................................................................................................................... 87 14.1.38 P_SERR_L EVENT DISABLE REGISTER - OFFSET 64h........................................ 87 14.1.39 GPIO DATA AND CONTROL REGISTER - OFFSET 64h ........................................ 88 14.1.40 SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h ................................. 88 14.1.41 P_SERR_L STATUS REGISTER - OFFSET 68h ........................................................ 89 14.1.42 PORT OPTION REGISTER - OFFSET 74h ................................................................ 90 14.1.43 RETRY COUNTER REGISTER - OFFSET 78h .......................................................... 91 Page 7 of 108 APRIL 2006 - Revision 2.02
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14.1.44 14.1.45 14.1.46 14.1.47 14.1.48 14.1.49 14.1.50 14.1.51 14.1.52 14.1.53 14.1.54 14.1.55 15
SECONDARY BUS MASTER TIMEOUT COUNTER - OFFSET 80h....................... 91 PRIMARY BUS MASTER TIMEOUT COUNTER - OFFSET 80h............................. 92 CAPABILITY ID REGISTER - OFFSET B0h ............................................................. 92 NEXT POINTER REGISTER - OFFSET B0h ............................................................. 92 SLOT NUMBER REGISTER - OFFSET B0h .............................................................. 92 CHASSIS NUMBER REGISTER - OFFSET B0h ....................................................... 93 CAPABILITY ID REGISTER - OFFSET DCh............................................................. 93 NEXT ITEM POINTER REGISTER - OFFSET DCh ................................................. 93 POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET DCh ................. 93 POWER MANAGEMENT DATA REGISTER - OFFSET E0h................................... 94 CAPABILITY ID REGISTER - OFFSET E4h ............................................................. 94 NEXT POINTER REGISTER - OFFSET E4h ............................................................. 94
BRIDGE BEHAVIOR.................................................................................................................... 95
15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 95 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 95 15.2.1 MASTER ABORT................................................................................................................ 95 15.2.2 PARITY AND ERROR REPORTING ................................................................................ 95 15.2.3 REPORTING PARITY ERRORS ....................................................................................... 96 15.2.4 SECONDARY IDSEL MAPPING ...................................................................................... 96 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 96
16.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 96 16.1.1 TAP PINS ............................................................................................................................ 97 16.1.2 INSTRUCTION REGISTER .............................................................................................. 97 16.2 BOUNDARY SCAN INSTRUCTION SET ................................................................................ 98 16.3 TAP TEST DATA REGISTERS.................................................................................................. 99 16.4 BYPASS REGISTER ................................................................................................................... 99 16.5 BOUNDARY-SCAN REGISTER................................................................................................ 99 16.6 TAP CONTROLLER ................................................................................................................... 99 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 18.2 18.3 ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 102 MAXIMUM RATINGS ............................................................................................................. 102 DC SPECIFICATIONS.............................................................................................................. 103 AC SPECIFICATIONS.............................................................................................................. 104 66MHZ TIMING........................................................................................................................ 104 33MHZ TIMING........................................................................................................................ 105 POWER CONSUMPTION ........................................................................................................ 105 PACKAGE INFORMATION...................................................................................................... 106 208-PIN FQFP PACKAGE DIAGRAM .................................................................................... 106 256-BALL PBGA PACKAGE DIAGRAM ............................................................................... 107 PART NUMBER ORDERING INFORMATION...................................................................... 107
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LIST OF TABLES
TABLE 2-1. PIN LIST - 208-PIN FQFP .......................................................................................................... 18 TABLE 2-2. PIN LIST - 256-PIN PBGA ......................................................................................................... 20 TABLE 3-1. PCI TRANSACTIONS ................................................................................................................... 22 TABLE 3-2. WRITE TRANSACTION FORWARDING......................................................................................... 23 TABLE 3-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES .................................................... 26 TABLE 3-4. READ PREFETCH ADDRESS BOUNDARIES .................................................................................. 28 TABLE 3-5. READ TRANSACTION PREFETCHING .......................................................................................... 28 TABLE 3-6. DEVICE NUMBER TO IDSEL S_AD PIN MAPPING..................................................................... 32 TABLE 3-7. DELAYED WRITE TARGET TERMINATION RESPONSE................................................................. 37 TABLE 3-8. RESPONSE TO POSTED WRITE TARGET TERMINATION............................................................... 37 TABLE 3-9. RESPONSE TO DELAYED READ TARGET TERMINATION ............................................................. 38 TABLE 5-1. SUMMARY OF TRANSACTION ORDERING ................................................................................... 48 TABLE 6-1. SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT .......................................... 56 TABLE 6-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ............................................ 56 TABLE 6-3. SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT......................... 56 TABLE 6-4. SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT.................... 57 TABLE 6-5. ASSERTION OF P_PERR_L........................................................................................................ 58 TABLE 6-6. ASSERTION OF S_PERR_L........................................................................................................ 58 TABLE 6-7. ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS ............................................................ 59 TABLE 10-1. GPIO OPERATION ................................................................................................................... 68 TABLE 10-2. GPIO SERIAL DATA FORMAT.................................................................................................. 68 TABLE 11-1. POWER MANAGEMENT TRANSITIONS ...................................................................................... 70 TABLE 16-1. TAP PINS ................................................................................................................................ 98 TABLE 16-2. JTAG BOUNDARY REGISTER ORDER .................................................................................... 100
LIST OF FIGURES
FIGURE 8-1 SECONDARY ARBITER EXAMPLE............................................................................................ 64 FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM ................................................................................. 97 FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS ............................................................ 104 FIGURE 18-1 208-PIN FQFP PACKAGE OUTLINE..................................................................................... 106 FIGURE 18-2 256-PIN PBGA PACKAGE OUTLINE.................................................................................... 107
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1
INTRODUCTION
Product Description
The PI7C8150B is an enhanced PCI-to-PCI Bridge that will support asynchronous operation and is designed to be fully compliant with the PCI Local Bus Specification Revision 2.3. Both the primary and secondary interfaces are specified to run at 32-bits and up to 66MHz (33MHz for PI7C8150B-33).
Product Features
* * * * 32-bit Primary and Secondary Ports run up to 66MHz (33MHz for PI7C8150B-33) Compliant with the PCI Local Bus Specification, Revision 2.3 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration write to special cycle conversion Compliant with the Advanced Configuration Power Interface (ACPI) Specification. Compliant with the PCI Power Management Specification, Revision 1.0. Synchronous and Asynchronous operation support - Supported modes of asynchronous operation Primary (MHz) PI7C8150B 25MHz to 66MHz PI7C8150B-33 25MHz to 33MHz Supported modes of synchronous operation Primary (MHz) PI7C8150B 66 PI7C8150B 66 PI7C8150B 50 PI7C8150B 50 PI7C8150B 33 PI7C8150B-33 PI7C8150B 25 PI7C8150B-33
* * *
Secondary (MHz) 25MHz to 66MHz 25MHz to 33MHz
-
Secondary (MHz) 66 33 50 25 33 25
* * * * * * * * *
Provides internal arbitration for one set of nine secondary bus masters - Programmable 2-level priority arbiter - Disable control for use of external arbiter Supports posted write buffers in all directions Four 128 byte FIFO's for delay transactions Two 128 byte FIFO's for posted memory transactions Enhanced address decoding Temperature support - Extended Commercial range 0C to 85C - Industrial range -40C to 85C IEEE 1149.1 JTAG interface support 3.3V core; 3.3V and 5V signaling Packaging: 208-pin FQFP and 256-pin PBGA - Pb-free & Green
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2
2.1
SIGNAL DEFINITIONS
Signal Types
Signal Type I O P TS STS OD Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain
2.2
Signals
Note: Signal names that end with "_L" are active LOW.
2.2.1
PRIMARY BUS INTERFACE SIGNALS
Name P_AD[31:0] Pin # 49, 50, 55, 57, 58, 60, 61, 63, 67, 68, 70, 71, 73, 74, 76, 77, 93, 95, 96, 98, 99, 101, 107, 109, 112, 113, 115, 116, 118, 119, 121, 122 Pin # N3, T2, T4, N5, P5, T5, N6, R5, T6, P7, T7, R7, T8, P8, R8, T9, R12, P12, T14, R13, N12, T15, P16, N15, M14, M13, M15, L13, M16, L14, L15, L16 R6, R9, T13, N16 Type TS Description Primary Address / Data: Multiplexed address and data bus. Address is indicated by P_FRAME_L assertion. Write data is stable and valid when P_IRDY_L is asserted and read data is stable and valid when P_TRDY_L is asserted. Data is transferred on rising clock edges when both P_IRDY_L and P_TRDY_L are asserted. During bus idle, PI7C8150B drives P_AD to a valid logic level when P_GNT_L is asserted.
P_CBE[3:0]
64, 79, 92, 110
TS
P_PAR
90
N11
TS
P_FRAME_L
80
P9
STS
Primary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C8150B drives P_CBE[3:0] to a valid logic level when P_GNT_L is asserted. Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and P_PAR (i.e. an even number of 1's). P_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of P_FRAME_L) for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY_L is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY_L is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C8150B drives P_PAR to a valid logic level when P_GNT_L is asserted. Primary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of P_FRAME_L indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle.
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Name P_IRDY_L
Pin # 82
Pin # T10
Type STS
P_TRDY_L
83
R10
STS
P_DEVSEL_L
84
P10
STS
P_STOP_L
85
T11
STS
P_LOCK_L P_IDSEL
87 65
R11 P6
STS I
P_PERR_L
88
T12
STS
P_SERR_L
89
P11
OD
P_REQ_L
47
P2
TS
P_GNT_L
46
R1
I
P_RESET_L
43
P1
I
Description Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8150B waits for the assertion of this signal within 5 cycles of P_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary LOCK (Active LOW). Asserted by the master for multiple transactions to complete. Primary ID Select. Used as a chip select line for Type 0 configuration access to PI7C8150B configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C8150B drives this pin on: Address parity error Posted write data parity error on target bus Secondary S_SERR_L asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW): This is asserted by PI7C8150B to indicate that it wants to start a transaction on the primary bus. PI7C8150B de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW): When asserted, PI7C8150B can access the primary bus. During idle and P_GNT_L asserted, PI7C8150B will drive P_AD, P_CBE, and P_PAR to valid logic levels. Primary RESET (Active LOW): When P_RESET_L is active, all PCI signals should be asynchronously tristated.
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Name P_M66EN
Pin # 102
Pin # R14
Type I
Description Primary Interface 66MHz Operation. This input is used to specify if PI7C8150B is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled "HIGH". For 33MHz operation on the Primary bus, this signal should be pulled LOW. In synchronous mode, S_M66EN will be driven LOW, forcing the secondary bus to run at 33MHz also. Also, bit [21] offset 04h is determined by CFG66. If P_M66EN is LOW, S_M66EN will not be driven LOW (please see S_M66EN pin description). In asynchronous mode, the logic value of P_M66EN is used to generate the value of bit[21] offset 04h.
2.2.2
SECONDARY BUS INTERFACE SIGNALS
Name S_AD[31:0] Pin # 206, 204, 203, 201, 200, 198, 197, 195, 192, 191, 189, 188, 186, 185, 183, 182, 165, 164, 162, 161, 159, 154, 152, 150, 147, 146, 144, 143, 141, 140, 138, 137 194, 180, 167, 149 Pin # A4, D5, C5, A5, B5, D6, A6, C6, C7, A7, B7, C8, A8, B8, A9, C9, C12, D12, A14, B13, A15, B16, E13, C16, E14, D16, F13, E16, F14, F15, F16, G16 B6, B9, B12, E15 Type TS Description Secondary Address/Data: Multiplexed address and data bus. Address is indicated by S_FRAME_L assertion. Write data is stable and valid when S_IRDY_L is asserted and read data is stable and valid when S_IRDY_L is asserted. Data is transferred on rising clock edges when both S_IRDY_L and S_TRDY_L are asserted. During bus idle, PI7C8150B drives S_AD to a valid logic level when S_GNT_L is asserted respectively.
S_CBE[3:0]
TS
S_PAR
168
A13
TS
S_FRAME_L
179
A10
STS
S_IRDY_L
177
B10
STS
S_TRDY_L
176
C10
STS
Secondary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C8150B drives S_CBE[3:0] to a valid logic level when the internal grant is asserted. Secondary Parity: Parity is even across S_AD[31:0], S_CBE[3:0], and S_PAR (i.e. an even number of 1's). S_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of S_FRAME_L) for address parity. For write data phases, S_PAR is an input and is valid one clock after S_IRDY_L is asserted. For read data phase, S_PAR is an output and is valid one clock after S_TRDY_L is asserted. Signal S_PAR is tri-stated one cycle after the S_AD lines are tri-stated. During bus idle, PI7C8150B drives S_PAR to a valid logic level when the internal grant is asserted. Secondary FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of S_FRAME_L indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle.
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Name S_DEVSEL_L
Pin # 175
Pin # A11
Type STS
S_STOP_L
173
B11
STS
S_LOCK_L S_PERR_L
172 171
C11 A12
STS STS
S_SERR_L
169
D11
I
S_REQ_L[8:0]
9, 8, 7, 6, 5, 4, 3, 2, 207
E4, E3, D2, C1, C2, D3, A2,B3, B4 G1, F1, F2, G3, F4, E1, E2,F3, D1
I
S_GNT_L[8:0]
19, 18, 17, 16, 15, 14, 13, 11, 10
TS
S_RESET_L
22
H1
O
S_M66EN
153
D15
I/OD
Description Secondary Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8150B waits for the assertion of this signal within 5 cycles of S_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary LOCK (Active LOW): Asserted by the master for multiple transactions to complete. Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the secondary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW): This is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. Secondary Grant (Active LOW): PI7C8150B asserts this pin to access the secondary bus. PI7C8150B deasserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT_L asserted, PI7C8150B will drive S_AD, S_CBE, and S_PAR. Secondary RESET (Active LOW): Asserted when any of the following conditions are met: 1. Signal P_RESET_L is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. When asserted, all control signals are tri-stated and zeroes are driven on S_AD, S_CBE, and S_PAR. Secondary Interface 66MHz Operation: In synchronous mode, this input is used to specify if PI7C8150B is running at 66MHz on the secondary side. When HIGH, the Secondary bus may run at 66MHz. When LOW, the Secondary bus may only run at 33MHz. If P_M66EN is pulled LOW, the S_M66EN is also driven LOW. In asynchronous mode, S_M66EN is an input pin and operates independently from P_M66EN. S_M66EN should be pulled up to a logic "1" when the secondary frequency is 66MHz, or pulled down to a logic "0" when the secondary frequency is 33MHz. Secondary Bus Central Function Control Pin: When tied LOW, it enables the internal arbiter. When tied HIGH, an external arbiter must be used. S_REQ_L[0] is reconfigured to be the secondary bus grant input, and S_GNT_L[0] is reconfigured to be the secondary bus request output. S_CFN_L has a weak internal pulldown resistor.
S_CFN_L
23
H2
I
2.2.3
CLOCK SIGNALS
Name P_CLK S_CLKIN Pin # 45 21 Pin # M4 H3 Type I I Description Primary Clock Input: Provides timing for all transactions on the primary interface. Secondary Clock Input: Provides timing for all transactions on the secondary interface.
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Name S_CLKOUT[9:0]
Pin # 42, 41, 39, 38, 36, 35, 33, 32, 30, 29
Pin # M3, M2, N1, L4, L3, M1, L2, L1, K3, K2
Type O
Description Secondary Clock Output: Provides secondary clocks phase synchronous with the P_CLK in synchronous mode. When these clocks are used, one of the clock outputs must be fed back to S_CLKIN. Unused outputs may be disabled by: 1. Writing the secondary clock disable bits in the configuration space 2. Using the serial disable mask using the GPIO pins and MSK_IN 3. Terminating them electrically. In asynchronous mode, S_CLKOUT[5:0] are derived from MSK_IN / ASYNC_CLKIN (please see CFG66 / SCAN_EN_H / CLK_RATE pin description).
2.2.4
MISCELLANEOUS SIGNALS
Name MSK_IN / ASYNC_CLKIN Pin # 126 Pin # K15 Type I Description This is a multiplexed pin that is MSK_IN in synchronous mode and ASYNC_CLK_IN in asynchronous mode. This pin has a weak internal pulldown resistor. MSK_IN - Secondary Clock Disable Serial Input (synchronous mode): This pin is used by PI7C8150B to disable secondary clock outputs. The serial stream is received by MSK_IN, starting when P_RESET is detected deasserted and S_RESET_L is detected as being asserted. The serial data is used for selectively disabling secondary clock outputs and is shifted into the secondary clock control configuration register. This pin can be tied LOW to enable all secondary clock outputs or tied HIGH to drive all the secondary clock outputs HIGH. ASYNC_CLKIN - Secondary Clock Input (asynchronous mode): The asynchronous clock for the secondary interface should be connected to this pin in asynchronous mode. S_CLKOUT[9:0] will be derived from ASYNC_CLKIN. Primary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the primary bus. P_VIO must be tied to 3.3V only when all devices on the primary bus use 3.3V signaling. Otherwise, P_VIO is tied to 5V. Secondary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the secondary bus. S_VIO must be tied to 3.3V only when all devices on the secondary bus use 3.3V signaling. Otherwise, S_VIO is tied to 5V. Bus/Power Clock Control Management Pin: When this pin is tied HIGH and the PI7C8150B is placed in the D3HOT power state, it enables the PI7C8150B to place the secondary bus in the B2 power state. The secondary clocks are disabled and driven to 0. When this pin is tied LOW, there is no effect on the secondary bus clocks when the PI7C8150B enters the D3HOT power state.
P_VIO
124
K14
I
S_VIO
135
G14
I
BPCCE
44
N2
I
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CFG66 / SCAN_EN_H / CLK_RATE
125
K16
I
This is a multiplexed pin that has 3 functions (2 in synchronous mode and 1 in asynchronous mode). CFG66 - 66MHz Configuration (synchronous mode): This pin is used to designate 66MHz operation. Tie HIGH to enable 66MHz operation or tie LOW to designate 33MHz operation. SCAN_EN_H - Full-Scan Enable Control (synchronous mode): When SCAN_EN_H is LOW, full-scan is in shift operation. When SCAN_EN_H is HIGH, full-scan is in parallel operation. Note: Valid only in test mode. Pin is CFG66 in normal operation. CLK_RATE - S_CLKOUT divider (asynchronous mode): Determines the S_CLKOUT frequency relation to ASYNC_CLK_IN. 0: S_SCLKOUT is half the frequency of ASYNC_CLK_IN. 1: S_CLKOUT is the same frequency as ASYNC_CLK_IN. Mode Selection: Selector for Asynchronous or Synchronous mode. MS0 0 0 1 1 MS1 0 1 0 1 Description RESERVED RESERVED Synchronous Mode Asynchronous Mode
MS0, MS1
155, 106
B14, R16
I
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name GPIO[3:0] Pin # 24, 25, 27, 28 Pin # J3, J2, J1, K1 Type TS Description General Purpose I/O Data Pins: The 4 generalpurpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space.
2.2.6
JTAG BOUNDARY SCAN SIGNALS
Name TCK TMS TDO Pin # 133 132 130 Pin # H15 H14 H16 Type I I O Description Test Clock. Used to clock state information and data into and out of the PI7C8150B during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. When SCAN_EN_H is HIGH, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. Test Data Input. When SCAN_EN_H is HIGH, it is used (in conjunction with TCK) to shift data and instructions into the Test Access Port (TAP) in a serial bit stream. Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state.
TDI
129
J15
I
TRST_L
134
G15
I
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2.2.7
POWER AND GROUND
Name VDD Pin # 1, 26, 34, 40, 51, 53, 56, 62, 69, 75, 81, 91, 97, 103, 105, 108, 114, 120, 131, 139, 145, 151, 157, 163, 170, 178, 184, 190, 196, 202, 208 Pin # A3, C4, C15, D7, D8, D9, D10, E6, E7, E8, E9, E10, E11, F5, F12, G4, G5, G12, G13, H4, H5, H12, H13, J4, J5, J12, J13, K4, K5, K12, K13, L5, L12, M6, M7, M8, M9, M10, M11, N7, N8, N9, N10, P13, P15, R3, T3 A1, A16, B1, B2, B15, C3, C13, C14, D4, D13, D14, E5, E12, F6, F7, F8, F9, F10, F11, G2, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L6, L7, L8, L9, L10, L11, M5, M12, N4, N13, N14, P3, P4, P14, R2, R4, R15, T1, T16 Type P Description Power: +3.3V Digital power.
VSS
12, 20, 31, 37, 48, 52, 54, 59, 66, 72, 78, 86, 94, 100, 104, 111, 117, 123, 136, 142, 148, 156, 158, 160, 166, 174, 181, 187, 193, 199, 205
P
Ground: Digital ground.
2.3
PIN LIST - 208-PIN FQFP
Table 2-1. Pin List - 208-pin FQFP
Pin Number 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Name VDD S_REQ_L[2] S_REQ_L[4] S_REQ_L[6] S_REQ_L[8] S_GNT_L[1] S_GNT_L[2] S_GNT_L[4] S_GNT_L[6] S_GNT_L[8] S_CLKIN S_CFN_L GPIO[2] GPIO[1] S_CLKOUT[0] VSS S_CLKOUT[3] Type P I I I I TS TS TS TS TS I I TS TS O P O Pin Number 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Name S_REQ_L[1] S_REQ_L[3] S_REQ_L[5] S_REQ_L[7] S_GNT_L[0] VSS S_GNT_L[3] S_GNT_L[5] S_GNT_L[7] VSS S_RESET_L GPIO[3] VDD GPIO[0] S_CLKOUT[1] S_CLKOUT[2] VDD Type I I I I TS P TS TS TS P O TS P TS O O P
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Pin Number 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159
Name S_CLKOUT[4] VSS S_CLKOUT[7] S_CLKOUT[8] P_RESET_L P_CLK P_REQ_L P_AD[31] VDD VDD P_AD[29] P_AD[28] VSS P_AD[25] P_AD[24] P_IDSEL P_AD[23] VDD P_AD[20] P_AD[19] VDD P_AD[16] P_CBE[2] VDD P_TRDY_L P_STOP_L P_LOCK_L P_SERR_L VDD P_AD[15] P_AD[14] VDD P_AD[11] P_AD[10] VDD VDD P_AD[9] P_AD[8] VSS P_AD[6] P_AD[5] VSS P_AD[2] P_AD[1] VSS CFG66 / SCAN_EN_H / CLK_RATE RESERVED TDI VDD TCK S_VIO S_AD[0] VDD S_AD[3] S_ADD[4] VDD S_AD[7] S_CBE[0] VDD S_M66EN MS0 VDD S_AD[11]
Type O P O O I I TS TS P P TS TS P TS TS I TS P TS TS P TS TS P STS STS STS STS P TS TS P TS TS P P TS TS P TS TS P TS TS P I I P I I TS P TS TS P TS TS P I/OD I P TS
Pin Number 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160
Name S_CLKOUT[5] S_CLKOUT[6] VDD S_CLKOUT[9] BPCCE P_GNT_L VSS P_AD[30] VSS VSS VDD P_AD[27] P_AD[26] VDD P_CBE[3] VSS P_AD[22] P_AD[21] VSS P_AD[18] P_AD[17] VSS P_FRAME_L P_IRDY_L P_DEVSEL_L VSS P_PERR_L P_PAR P_CBE[1] VSS P_AD[13] P_AD[12] VSS P_M66EN VSS MS1 VDD P_CBE[0] P_AD[7] VDD P_AD[4] P_AD[3] VDD P_AD[0] P_VIO MSK_IN ASYNC_CLK_IN RESERVED TDO TMS TRST_L VSS S_AD[1] S_AD[2] VSS S_AD[5] S_AD[6] VSS S_AD[8] S_AD[9] S_AD[10] VSS VSS VSS
Type O O P O I I P TS P P P TS TS P TS P TS TS P TS TS P STS STS STS P STS STS TS P TS TS P I P I P TS TS P TS TS P TS I I O I I P TS TS P TS TS P TS TS TS P P P
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Pin Number 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207
Name S_AD[12] VDD S_AD[15] S_CBE[1] S_SERR_L S_PERR_L S_STOP_L S_DEVSEL_L S_IRDY_L S_FRAME_L VSS S_AD[17] S_AD[18] VSS S_AD[21] S_AD[22] VSS S_AD[24] S_AD[25] VSS S_AD[28] S_AD[29] VSS S_REQ_L[0]
Type TS P TS TS I STS STS STS STS STS P TS TS P TS TS P TS TS P TS TS P I
Pin Number 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208
Name S_AD[13] S_AD[14] VSS S_PAR VDD S_LOCK_L VSS S_TRDY_L VDD S_CBE[2] S_AD[16] VDD S_AD[19] S_AD[20] VDD S_AD[23] S_CBE[3] VDD S_AD[26] S_AD[27] VDD S_AD[30] S_AD[31] VDD
Type TS TS P TS P STS P STS P TS TS P TS TS P TS TS P TS TS P TS TS P
2.4
PIN LIST - 256-BALL PBGA
Table 2-2. Pin List - 256-pin PBGA
Pin Number A1 A4 A7 A10 A13 A16 B3 B6 B9 B12 B15 C2 C5 C8 C11 C14 D1 D4 D7 D10 D13 D16 E3 E6 E9 E12 E15 F2 F5 F8 Name VSS S_AD[31] S_AD[22] S_FRAME_L S_PAR VSS S_REQ_L[1] S_CBE_L[3] S_CBE_L[2] S_CBE_L[1] VSS S_REQ_L[4] S_AD[29] S_AD[20] S_LOCK_L VSS S_GNT_L[0] VSS VDD VDD VSS S_AD[6] S_REQ_L[7] VDD VDD VSS S_CBE_L[0] S_GNT_L[6] VDD VSS Type P TS TS STS TS P I TS TS TS P I TS TS STS P TS P P P P TS I P P P TS TS P P Pin Number A2 A5 A8 A11 A14 B1 B4 B7 B10 B13 B16 C3 C6 C9 C12 C15 D2 D5 D8 D11 D14 E1 E4 E7 E10 E13 E16 F3 F6 F9 Name S_REQ_L[2] S_AD[28] S_AD[19] S_DEVSEL_L S_AD[13] VSS S_REQ_L[0] S_AD[21] S_IRDY_L S_AD[12] S_AD[10] VSS S_AD[24] S_AD[16] S_AD[15] VDD S_REQ_L[6] S_AD[30] VDD S_SERR_L VSS S_GNT_L[3] S_REQ_L[8] VDD VDD S_AD[9] S_AD[4] S_GNT_L[1] VSS VSS Type I TS TS STS TS P I TS STS TS TS P TS TS TS P I TS P I P TS I P P TS TS TS P P Pin Number A3 A6 A9 A12 A15 B2 B5 B8 B11 B14 C1 C4 C7 C10 C13 C16 D3 D6 D9 D12 D15 E2 E5 E8 E11 E14 F1 F4 F7 F10 Name VDD S_AD[25] S_AD[17] S_PERR_L S_AD[11] VSS S_AD[27] S_AD[18] S_STOP_L MS0 S_REQ_L[5] VDD S_AD[23] S_TRDY_L VSS S_AD[8] S_REQ_L[3] S_AD[26] VDD S_AD[14] S_M66EN S_GNT_L[2] VSS VDD VDD S_AD[7] S_GNT_L[7] S_GNT_L[4] VSS VSS Type P TS TS STS TS P TS TS STS P I P TS STS P TS I TS P TS I/OD TS P P P TS TS TS P P
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Pin Number F11 F14 G1 G4 G7 G10 G13 G16 H3 H6 H9 H12 H15 J2 J5 J8 J11 J14 K1 K4 K7 K10 K13 K16
Name VSS S_AD[3] S_GNT_L[8] VDD VSS VSS VDD S_AD[0] S_CLKIN VSS VSS VDD TCK GPIO[2] VDD VSS VSS RESERVED GPIO[0] VDD VSS VSS VDD CFG66 SCAN_EN_H CLK_RATE S_CLKOUT[5] VSS VSS VSS P_AD[4] P_AD[0] S_CLKOUT[9] VDD VDD VSS P_AD[5] BPCCE P_AD[28] VDD P_PAR VSS P_RESET_L VSS P_AD[22] P_DEVSEL_L VDD P_AD[9] VDD P_CBE_L[3] P_CBE_L[2] P_AD[15] VSS P_AD[30] P_AD[26] P_AD[19] P_STOP_L P_AD[13]
Type P TS TS P P P P TS I P P P I TS P P P TS P P P P I
Pin Number F12 F15 G2 G5 G8 G11 G14 H1 H4 H7 H10 H13 H16 J3 J6 J9 J12 J15 K2 K5 K8 K11 K14 L1
Name VDD S_AD[2] VSS VDD VSS VSS S_VIO S_RESET_L VDD VSS VSS VDD TDO GPIO[3] VSS VSS VDD TDI S_CLKOUT[0] VDD VSS VSS P_VIO S_CLKOUT[2]
Type P TS P P P P I O P P P P O TS P P P I O P P P I O
Pin Number F13 F16 G3 G6 G9 G12 G15 H2 H5 H8 H11 H14 J1 J4 J7 J10 J13 J16 K3 K6 K9 K12 K15 L2
Name S_AD[5] S_AD[1] S_GNT_L[5] VSS VSS VDD TRST_L S_CFN_L VDD VSS VSS TMS GPIO[1] VDD VSS VSS VDD RESERVED S_CLKOUT[1] VSS VSS VDD MSK_IN
ASYNC_CLK_IN
Type TS TS TS P P P I I P P P I TS P P P P O P P P I O
S_CLKOUT[3]
L3 L6 L9 L10 L13 L16 M3 M6 M9 M12 M15 N2 N5 N8 N11 N14 P1 P4 P7 P10 P13 P16 R3 R6 R9 R12 R15 T2 T5 T8 T11 T14
O P P P TS TS O P P P TS I TS P TS P I P TS STS P TS P TS TS TS P TS TS TS STS TS
L4 L7 L11 L14 M1 M4 M7 M10 M13 M16 N3 N6 N9 N12 N15 P2 P5 P8 P11 P14 R1 R4 R7 R10 R13 R16 T3 T6 T9 T12 T15
S_CLKOUT[6] VSS VSS P_AD[2] S_CLKOUT[4] P_CLK VDD VDD P_AD[6] P_AD[3] P_AD[31] P_AD[25] VDD P_AD[11] P_AD[8] P_REQ_L P_AD[27] P_AD[18] P_SERR_L VSS P_GNT_L VSS P_AD[20] P_TRDY_L P_AD[12] MS1 VDD P_AD[23] P_AD[16] P_PERR_L P_AD[10]
O P P TS O I P P TS TS TS TS P TS TS TS TS TS OD P I P TS STS TS P P TS TS STS TS
L5 L8 L12 L15 M2 M5 M8 M11 M14 N1 N4 N7 N10 N13 N16 P3 P6 P9 P12 P15 R2 R5 R8 R11 R14 T1 T4 T7 T10 T13 T16
VDD VSS VDD P_AD[1] S_CLKOUT[8] VSS VDD VDD P_AD[7] S_CLKOUT[7] VSS VDD VDD VSS P_CBE_L[0] VSS P_IDSEL P_FRAME_L P_AD[14] VDD VSS P_AD[24] P_AD[17] P_LOCK_L P_M66EN VSS P_AD[29] P_AD[21] P_IRDY_L P_CBE_L[1] VSS
P P P TS O P P P TS O P P P P TS P I STS TS P P TS TS STS I P TS TS STS TS P
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3
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO's for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables that are used for write transactions. The PI7C8150B also has an additional four 128-byte FIFO's that hold addresses, data, commands, and byte enables for read transactions.
3.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150B. Table 3-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8150B initiates transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B responds to transactions as a target, on the primary (P) and secondary (S) buses. Table 3-1. PCI Transactions
Types of Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Initiates as Master Primary N Y Y Y N N Y Y N N N Y (Type 1 only) Y Y Y Y Secondary N Y Y Y N N Y Y N N Y Y Y Y Y Y Responds as Target Primary Secondary N N N N Y Y Y Y N N N N Y Y Y Y N N N N Y N Y Y (Type 1 only) Y Y Y Y Y Y Y Y
As indicated in Table 3-1, the following PCI commands are not supported by PI7C8150B: PI7C8150B never initiates a PCI transaction with a reserved command code and, as a target, PI7C8150B ignores reserved command codes. PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B ignores interrupt acknowledge transactions as a target. PI7C8150B does not respond to special cycle transactions. PI7C8150B cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. PI7C8150B neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses. Page 22 of 108 APRIL 2006 - Revision 2.02
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3.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C8150B supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C8150B automatically disconnects the transaction after the first data transfer.
3.3
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8150B always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C8150B never does subtractive decode.
3.4
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted. A transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is deasserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L are asserted. See Section 3.8 for further discussion of transaction termination. Depending on the command type, PI7C8150B can support multiple data phase PCI transactions. For detailed descriptions of how PI7C8150B imposes disconnect boundaries, see Section 3.5.4 for write address boundaries and Section 3.6.3 read address boundaries.
3.5
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 3-2 shows the method of forwarding used for each type of write operation. Table 3-2. Write Transaction Forwarding
Type of Transaction Memory Write Memory Write and Invalidate Memory Write to VGA memory I/O Write Type 1 Configuration Write Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed Delayed
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3.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for "Memory Write" and "Memory Write and Invalidate" transactions. When PI7C8150B determines that a memory write transaction is to be forwarded across the bridge, PI7C8150B asserts DEVSEL_L with medium timing and TRDY_L in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C8150B accepts write data without obtaining access to the target bus. The PI7C8150B can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C8150B continues to accept write data until one of the following events occurs: The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up. When one of the last two events occurs, the PI7C8150B returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C8150B asserts its request on the target bus. This can occur while PI7C8150B is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C8150B asserts FRAME_L and drives the stored write address out on the target bus. On the following cycle, PI7C8150B drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C8150B can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C8150B and the initiator stalls, PI7C8150B will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C8150B will restart the follow-on transactions if the queue has new data. PI7C8150B ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C8150B starts another transaction to deliver the rest of the write data). The target returns a target abort (PI7C8150B discards remaining write data). The master latency timer expires, and PI7C8150B no longer has the target bus grant (PI7C8150B starts another transaction to deliver remaining write data). Section 3.8.3.2 provides detailed information about how PI7C8150B responds to target termination during posted write transactions.
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3.5.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions. If offset 74h bits [8:7] = 11, the PI7C8150B disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If offset 74h bits [8:7] = 00, the PI7C8150b converts Memory Write and Invalidate transactions to Memory Write transactions at the destination. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C8150B returns a target disconnect to the initiator on a cache line boundary.
3.5.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and PI7C8150B forwards it as a delayed transaction, PI7C8150B claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150B samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150B also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150B initiates the transaction on the target bus. PI7C8150B transfers the write data to the target. If PI7C8150B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C8150B is unable to deliver write data after 224 (default) or 232 (maximum) attempts, PI7C8150B will report a system error. PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section 6.4 for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C8150B claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150B also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared.
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If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150B does not make a new entry into the delayed transaction queue. Section 3.8.3.1 provides detailed information about how PI7C8150B responds to target termination during delayed write transactions. PI7C8150B implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C8150B discards the delayed write completion from the delayed transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L (see Section 6.4).
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8150B imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150B from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 3-3. Table 3-3. Write Transaction Disconnect Address Boundaries
Type of Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write and Invalidate Posted Memory Write and Invalidate Condition All Memory write disconnect control bit = 0(1) Memory write disconnect control bit = 1(1) Cache line size 1, 2, 4, 8, 16 Cache line size = 1, 2, 4, 8, 16 Aligned Address Boundary Disconnects after one data transfer 4KB aligned address boundary Disconnects at cache line boundary 4KB aligned address boundary
Cache line boundary if posted memory write data FIFO does not have enough space for the cache line Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space.
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8150B continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.
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3.5.6
FAST BACK-TO-BACK TRANSACTIONS
PI7C8150B can recognize and post fast back-to-back write transactions. When PI7C8150B cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
3.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation.
3.6.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8150B performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C8150B forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C8150B, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFO's, and so on. The target device's base address register or registers indicate if a memory address region is prefetchable.
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8150B requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C8150B forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior. Page 27 of 108 APRIL 2006 - Revision 2.02
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3.6.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C8150B imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C8150B stops prefetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C8150B finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flowthrough mode during read operations. Table 3-4 shows the read pre-fetch address boundaries for read transactions during nonflow-through mode. Table 3-4. Read Prefetch Address Boundaries
Type of Transaction Configuration Read I/O Read Memory Read Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Address Space Non-Prefetchable Prefetchable Prefetchable Cache Line (CLS) * * * CLS = 0 or 16 Size Prefetch Aligned Address Boundary One DWORD (no prefetch) One DWORD (no prefetch) One DWORD (no prefetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary 2X of cache line boundary
CLS = 1, 2, 4, 8, 16 CLS = 0 or 16 CLS = 1, 2, 4, 8, 16 CLS = 0 or 16
Memory Read Multiple CLS = 1, 2, 4, 8, 16 - does not matter if it is prefetchable or non-prefetchable * don't care
Table 3-5. Read Transaction Prefetching
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used if address is prefetchable space Memory Read Upstream: Prefetching used or programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces. Type of Transaction I/O Read Configuration Read
3.6.4
DELAYED READ REQUESTS
PI7C8150B treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction.
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When PI7C8150B accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY_L is asserted, PI7C8150B then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C8150B terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.
3.6.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue, PI7C8150B arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C8150B uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, PI7C8150B drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150B receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C8150B does not initiate any further attempts to read more data. If PI7C8150B is unable to obtain read data from the target after 224 (default) or 232 (maximum) attempts, PI7C8150B will report system error. The number of attempts is programmable. PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section 6.4 for information on the assertion of P_SERR_L. Once PI7C8150B receives DEVSEL_L and TRDY_L from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C8150B can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD's transferred during a delayed read transaction depends on the conditions given in Table 3-4 (assuming no disconnect is received from the target).
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150B transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C8150B aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150B returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150B initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read Page 29 of 108 APRIL 2006 - Revision 2.02
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boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150B reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150B will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data will be discarded even though the master timeout timer has not expired. PI7C8150B implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires (215 default), PI7C8150B discards the read transaction and read data from its queues. PI7C8150B also conditionally asserts P_SERR_L (see Section 6.4). PI7C8150B has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150B.
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C8150B can recognize fast back-to-back read transactions.
3.7
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150B also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 Page 30 of 108 APRIL 2006 - Revision 2.02
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configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.
3.7.1
TYPE 0 ACCESS TO PI7C8150B
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150B responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase: The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted. PI7C8150B limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150B ignores all Type 0 transactions initiated on the secondary interface.
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150B must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C8150B generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase:
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The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When PI7C8150B translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the lowest two address bits on S_AD[1:0]. Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device's IDSEL signal. Sets S_AD[15:11] to 0. Leaves unchanged the function number and register number fields. PI7C8150B asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. presents the mapping that PI7C8150B uses. Table 3-6. Device Number to IDSEL S_AD Pin Mapping
Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h - 1Eh 1Fh P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 - 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] > 00h) 0000 0000 0000 0000 (P_AD[7:2] = 00h) S_AD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -
PI7C8150B can assert up to 9 unique address lines to be used as IDSEL signals for up to 9 devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary. However, if device numbers greater than 9 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort.
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PI7C8150B forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
3.7.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C8150B detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C8150B forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: The lowest two address bits are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction. PI7C8150B also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: The lowest two address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The bus command is a configuration write transaction. The PI7C8150B forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer.
3.7.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction.
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PI7C8150B initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. The bus command on CBE_L is a configuration write command. When PI7C8150B initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C8150B responds with TRDY_L to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, PI7C8150B responds with a target disconnect operation during the first data phase.
3.8
TRANSACTION TERMINATION
This section describes how PI7C8150B returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: Normal termination Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY_L or STOP_L assertion from the target. Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the initiator terminates the transaction with a master abort. If FRAME_L is still asserted, the initiator de-asserts FRAME_L on the next cycle, and then de-asserts IRDY_L on the following cycle. IRDY_L must be asserted in the same cycle in which FRAME_L deasserts. If FRAME_L is already de-asserted, IRDY_L can be de-asserted on the next clock cycle following detection of the master abort condition.
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The target can terminate transactions with one of the following types of termination: Normal termination TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L de-asserted and IRDY_L asserted. Target retry STOP_L and DEVSEL_L asserted with TRDY_L de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. Target disconnect with data transfer STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of the transaction. Target disconnect without data transfer STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. Target abort STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL_L must be asserted for at least one cycle during the transaction before the target abort is signaled.
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150B
PI7C8150B, as an initiator, uses normal termination if DEVSEL_L is returned by target within five clock cycles of PI7C8150B's assertion of FRAME_L on the target bus. As an initiator, PI7C8150B terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. For a posted write transaction, all write data for the transaction is transferred from data buffers to the target. For burst transfer, with the exception of "Memory Write and Invalidate" transactions, the master latency timer expires and the PI7C8150B's bus grant is de-asserted. The target terminates the transaction with a retry, disconnect, or target abort. If PI7C8150B is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered. If PI7C8150B is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data.
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3.8.2
MASTER ABORT RECEIVED BY PI7C8150B
If the initiator initiates a transaction on the target bus and does not detect DEVSEL_L returned by the target within five clock cycles of the assertion of FRAME_L, PI7C8150B terminates the transaction with a master abort. This sets the received-master-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, PI7C8150B is able to reflect the master abort condition back to the initiator. When PI7C8150B detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C8150B does not respond to the transaction with DEVSEL_L, which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C8150B discards the posted write data and makes no more attempts to deliver the data. PI7C8150B sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR_L enable bit (bit 8 of command register for secondary bus) are set, PI7C8150B asserts P_SERR_L if the master-abort-on-posted-write is not set. The masterabort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h). Note: When PI7C8150B performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150B
When PI7C8150B initiates a transaction on the target bus and the target responds with DEVSEL_L, the target can end the transaction with one of the following types of termination: Normal termination (upon de-assertion of FRAME_L) Target retry Target disconnect Target abort PI7C8150B handles these terminations in different ways, depending on the type of transaction being performed.
3.8.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8150B initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 3-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C8150B repeats a delayed write transaction until one of the following conditions is met: PI7C8150B completes at least one data transfer. PI7C8150B receives a master abort. PI7C8150B receives a target abort. Page 36 of 108 APRIL 2006 - Revision 2.02
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PI7C8150B makes 224 (default) or 232 (maximum) write attempts resulting in a response of target retry. Table 3-7. Delayed Write Target Termination Response
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target retry to initiator. Continue write attempts to target Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target abort to initiator. Set received target abort bit in target interface status register. Set signaled target abort bit in initiator interface status register.
After the PI7C8150B makes 224 (default) attempts of the same delayed write trans-action on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of system error conditions.
3.8.3.2
POSTED WRITE TARGET TERMINATION RESPONSE When PI7C8150B initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 3-8 shows the response to each type of target termination that occurs during a posted write transaction. Table 3-8. Response to Posted Write Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse No additional action. Repeating write transaction to target. Initiate write transaction for delivering remaining posted write data. Set received-target-abort bit in the target interface status register. Assert P_SERR# if enabled, and set the signaled-system-error bit in primary status register.
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C8150B initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C8150B will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt. After the PI7C8150B makes 224 (default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See Section 6.4 for a discussion of system error conditions.
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3.8.3.3
DELAYED READ TARGET TERMINATION RESPONSE When PI7C8150B initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 3-9 shows the response to each type of target termination that occurs during a delayed read transaction. PI7C8150B repeats a delayed read transaction until one of the following conditions is met: PI7C8150B completes at least one data transfer. PI7C8150B receives a master abort. PI7C8150B receives a target abort. PI7C8150B makes 224 (default) read attempts resulting in a response of target retry. Table 3-9. Response to Delayed Read Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Response If prefetchable, target disconnect only if initiator requests more data than read from target. If non-prefetchable, target disconnect on first data phase. Re-initiate read transaction to target If initiator requests more data than read from target, return target disconnect to initiator. Return target abort to initiator. Set received target abort bit in the target interface status register. Set signaled target abort bit in the initiator interface status register.
After PI7C8150B makes 224(default) attempts of the same delayed read transaction on the target bus, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of system error conditions.
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150B
PI7C8150B can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface.
3.8.4.1
TARGET RETRY PI7C8150B returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C8150B returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: The transaction is being entered into the delayed transaction queue. Transaction has already been entered into delayed transaction queue, but target response has not yet been received. Target response has been received but has not progressed to the head of the return queue. Page 38 of 108 APRIL 2006 - Revision 2.02
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The delayed transaction queue is full, and the transaction cannot be queued. A transaction with the same address and command has been queued. A locked sequence is being propagated across PI7C8150B, and the write transaction is not a locked transaction. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction. For delayed read transactions: The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at head of the read data queue or a posted write transaction precedes it. The delayed transaction queue is full, and the transaction cannot be queued. A delayed read request with the same address and bus command has already been queued. A locked sequence is being propagated across PI7C8150B, and the read transaction is not a locked transaction. PI7C78150B is currently discarding previously pre-fetched read data. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction. For posted write transactions: The posted write data buffer does not have enough space for address and at least one DWORD of write data. A locked sequence is being propagated across PI7C8150B, and the write transaction is not a locked transaction. When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers.
3.8.4.2
TARGET DISCONNECT PI7C8150B returns a target disconnect to an initiator when one of the following conditions is met: PI7C8150B hits an internal address boundary. Page 39 of 108 APRIL 2006 - Revision 2.02
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PI7C8150B cannot accept any more write data. PI7C8150B has no more read data to deliver. See Section 3.5.4 for a description of write address boundaries, and Section 3.6.3 for a description of read address boundaries.
3.8.4.3
TARGET ABORT PI7C8150B returns a target abort to an initiator when one of the following conditions is met: PI7C8150B is returning a target abort from the intended target. When PI7C8150B returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.
4
ADDRESS DECODING
PI7C8150B uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGAaddressing support.
4.1
ADDRESS RANGES
PI7C8150B uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: Two 32-bit I/O address ranges Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges Two 32-bit prefetchable memory address ranges Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the secondary PCI bus to the primary PCI bus. No address translation is required in PI7C8150B. The addresses that are not marked for downstream are always forwarded upstream.
4.2
I/O ADDRESS DECODING
PI7C8150B uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding: Page 40 of 108 APRIL 2006 - Revision 2.02
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I/O base and limit address registers The ISA enable bit The VGA mode bit The VGA snoop bit This section provides information on the I/O address registers and ISA mode. Section 4.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the masterenable bit is not set, PI7C8150B ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions if it is set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, PI7C8150B response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
PI7C8150B implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C8150B supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C8150B to be mapped anywhere in a 4GB I/O address space. I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O trans-actions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that PI7C8150B supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h.
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The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.
4.2.2
ISA MODE
PI7C8150B supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C8150B inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C8150B when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, PI7C8150B does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, PI7C8150B forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C8150B can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
4.3
MEMORY ADDRESS DECODING
PI7C8150B has three mechanisms for defining memory address ranges for forwarding of memory transactions: Memory-mapped I/O base and limit address registers Prefetchable memory base and limit address registers VGA mode
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This section describes the first two mechanisms. Section 4.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set. CAUTION If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be pre-fetched but that can be conditionally pre-fetched based on command type should be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C8150B prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C8150B uses to determine when to forward memory commands. PI7C8150B forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. PI7C8150B ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism). The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space.
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To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register.
4.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C8150B pre-fetches for all types of memory read commands in this address space. The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C8150B uses to determine when to forward memory commands. PI7C8150B forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. PI7C8150B ignores memory transactions initiated on the secondary interface that fall into this address range. PI7C8150B does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the Page 44 of 108 APRIL 2006 - Revision 2.02
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upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32bit limit.
4.4
VGA SUPPORT
PI7C8150B provides two modes for VGA support: VGA mode, supporting VGA-compatible addressing VGA snoop mode, supporting VGA palette forwarding
4.4.1
VGA MODE
When a VGA-compatible device exists downstream from PI7C8150B, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C8150B is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. PI7C8150B ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h-000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8150B requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in the range of 3B0h-3BBh and 3C0h-3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0's. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
4.4.2
VGA SNOOP MODE
PI7C8150B provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C8150B needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C8150B claims VGA palette write transactions by asserting DEVSEL_L in VGA snoop mode. When VGA snoop bit is set, PI7C8150B forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space.
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Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8150B behaves in the same way as if only the VGA mode bit were set.
5
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8150B complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.3, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across PI7C8150B.
5.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing PI7C8150B: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C8150B does not combine or merge write transactions: PI7C8150B does not combine separate write transactions into a single write transaction--this optimization is best implemented in the originating master.
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PI7C8150B does not merge bytes on separate masked write transactions to the same DWORD address--this optimization is also best implemented in the originating master. PI7C8150B does not collapse sequential write transactions to the same address into a single write transaction--the PCI Local Bus Specification does not permit this combining of transactions.
5.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C8150B. The following general ordering guidelines govern transactions crossing PI7C8150B: The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C8150B can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150B and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C8150B accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150B.
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5.3
ORDERING RULES
Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 5-1. Summary of Transaction Ordering
Pass Posted Write No1 No2 No4 No3 Yes Delayed Read Request Yes5 Yes Yes Yes Yes Delayed Write Request Yes5 Yes Yes Yes Yes Delayed Read Completion Yes5 Yes Yes Yes Yes Delayed Write Completion Yes5 Yes Yes Yes Yes
Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C8150B's implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table 5-1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150B in the same direction. Note that delayed completion transactions cross PI7C8150B in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. A delayed read completion must ``pull'' ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150B as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data.
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5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.
5.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.3, provides the following alternative methods for synchronizing data and interrupts: The device signaling the interrupt performs a read of the data just written (software). The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C8150B does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.
6
ERROR HANDLING
PI7C8150B checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150B always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150B always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C8150B implements the following: PERR_L and SERR_L signals on both the primary and secondary interfaces Primary status and secondary status registers The device-specific P_SERR_L event disable register This chapter provides detailed information about how PI7C8150B handles errors. It also describes error status reporting and error operation disabling.
6.1
ADDRESS PARITY ERRORS
PI7C8150B checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8150B detects an address parity error on the primary interface, the following events occur:
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If the parity error response bit is set in the command register, PI7C8150B does not claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts the transaction if it is directed to or across PI7C8150B. PI7C8150B sets the detected parity error bit in the status register. PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register, if both the following conditions are met: The SERR_L enable bit is set in the command register. The parity error response bit is set in the command register. When PI7C8150B detects an address parity error on the secondary interface, the following events occur: If the parity error response bit is set in the bridge control register, PI7C8150B does not claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts transaction if it is directed to or across PI7C8150B. PI7C8150B sets the detected parity error bit in the secondary status register. PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met: The SERR_L enable bit is set in the command register. The parity error response bit is set in the bridge control register.
6.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8150B attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C8150B.
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE
When PI7C8150B detects a data parity error during a Type 0 configuration write transaction to PI7C8150B configuration space, the following events occur: If the parity error response bit is set in the command register, PI7C8150B asserts P_TRDY_L and writes the data to the configuration register. PI7C8150B also asserts P_PERR_L. If the parity error response bit is not set, PI7C8150B does not assert P_PERR_L.
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PI7C8150B sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
6.2.2
READ TRANSACTIONS
When PI7C8150B detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR_L. For downstream transactions, when PI7C8150B detects a read data parity error on the secondary bus, the following events occur: PI7C8150B asserts S_PERR_L two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. PI7C8150B sets the detected parity error bit in the secondary status register. PI7C8150B sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C8150B forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C8150B completes the transaction normally. For upstream transactions, when PI7C8150B detects a read data parity error on the primary bus, the following events occur: PI7C8150B asserts P_PERR_L two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. PI7C8150B sets the detected parity error bit in the primary status register. PI7C8150B sets the data parity detected bit in the primary status register, if the primary interface parity-error-response bit is set in the command register. PI7C8150B forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C8150B completes the transaction normally. PI7C8150B returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when PI7C8150B detects PERR_L asserted while returning read data to the initiator, PI7C8150B does not take any further action and completes the transaction normally.
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6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8150B detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR_L. For delayed write transactions, a parity error can occur at the following times: During the original delayed write request transaction When the initiator repeats the delayed write request transaction When PI7C8150B completes the delayed write transaction to the target When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When PI7C8150B detects a parity error on the write data for the initial delayed write request transaction, the following events occur: If the parity-error-response bit corresponding to the initiator bus is set, PI7C8150B asserts TRDY_L to the initiator and the transaction is not queued. If multiple data phases are requested, STOP_L is also asserted to cause a target disconnect. Two cycles after the data transfer, PI7C8150B also asserts PERR_L. If the parity-error-response bit is not set, PI7C8150B returns a target retry. It queues the transaction as usual. PI7C8150B does not assert PERR_L. In this case, the initiator repeats the transaction. PI7C8150B sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit. Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator's re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR_L assertion). For downstream transactions, when PI7C8150B is delivering data to the target on the secondary bus and S_PERR_L is asserted by the target, the following events occur: PI7C8150B sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C8150B captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when PI7C8150B is delivering data to the target on the primary bus and P_PERR_L is asserted by the target, the following events occur: PI7C8150B sets the primary interface data-parity-detected bit in the status register, if the primary parity-error-response bit is set in the command register.
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PI7C8150B captures the parity error condition to forward it back to the initiator on the secondary bus. A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered: When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8150B has write status to return, the following events occur: PI7C8150B first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if the primary interface parity-error-response bit is set in the command register. PI7C8150B sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8150B has write status to return, the following events occur: PI7C8150B first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). PI7C8150B sets the secondary interface parity-error-detected bit in the secondary status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the following are both true: The parity-error-response bit is set in the command register of the primary interface. The parity-error-response bit is set in the bridge control register of the secondary interface. PI7C8150B completes the transaction normally.
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For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the following are both true: The parity error response bit is set in the command register of the primary interface. The parity error response bit is set in the bridge control register of the secondary interface. PI7C8150B completes the transaction normally.
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150B responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C8150B sets the parity error detected bit in the status register of the primary interface. PI7C8150B captures and forwards the bad parity condition to the secondary bus. PI7C8150B completes the transaction normally. Similarly, during upstream posted write transactions, when PI7C8150B responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C8150B sets the parity error detected bit in the status register of the secondary interface. PI7C8150B captures and forwards the bad parity condition to the primary bus. PI7C8150B completes the transaction normally. During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target's assertion of S_PERR_L, the following events occur: PI7C8150B sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface.
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PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status register, if all the following conditions are met: The SERR_L enable bit is set in the command register. The posted write parity error bit of P_SERR_L event disable register is not set. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. PI7C8150B has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target's assertion of P_PERR_L, the following events occur: PI7C8150B sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status register, if all the following conditions are met: The SERR_L enable bit is set in the command register. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. PI7C8150B has not detected the parity error on the secondary (initiator) bus, which the parity error is not forwarded from the secondary bus to the primary bus. Assertion of P_SERR_L is used to signal the parity error condition when the initiator does not know that the error occurred. Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR_L will not be asserted.
6.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150B to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C8150B to data parity errors according to the status bits that PI7C8150B sets and the signals that it asserts. Table 6-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C8150B detects a parity error on the primary interface. Page 55 of 108 APRIL 2006 - Revision 2.02
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Table 6-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected Parity Error Bit Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
0 0 1 0 1 0 0 0 1 0 0 0 X = don't care
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity error on the secondary interface. Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Secondary Detected Parity Error Bit 0 1 0 0 0 0 0 1 0 0 0 1 X = don't care Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Table 6-3 shows setting data parity detected bit in the primary interface's status register. This bit is set under the following conditions: PI7C8150B must be a master on the primary bus. The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR_L signal is detected asserted or a parity error is detected on the primary bus. Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary Parity Bit Data Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits
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Primary Parity Bit
Data
Transaction Type
Direction
Bus Where Error Was Detected
0 0 1 0 0 0 1 0 0 0 1 0 X = don't care
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary / Secondary Parity Error Response Bits x/x x/x 1/x x/x x/x x/x 1/x x/x x/x x/x 1/x x/x
Table 6-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: The PI7C8150B must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR_L signal is detected asserted or a parity error is detected on the secondary bus. Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Secondary Detected Parity Detected Bit 0 1 0 0 0 1 0 0 0 1 0 0 X= don't care Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/1 x/x x/x x/x x/1 x/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions: PI7C8150B is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. PI7C8150B detects a data parity error on the primary bus or detects S_PERR_L asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.
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Table 6-5. Assertion of P_PERR_L
P_PERR_L Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits x/x x/x 1/x x/x 1/x x/x x/x x/x 1/x 1/1 x/x x/x
1 (de-asserted) Read Downstream Primary 1 Read Downstream Secondary 0 (asserted) Read Upstream Primary 1 Read Upstream Secondary 0 Posted Write Downstream Primary 1 Posted Write Downstream Secondary 1 Posted Write Upstream Primary 1 Posted Write Upstream Secondary 0 Delayed Write Downstream Primary 02 Delayed Write Downstream Secondary 1 Delayed Write Upstream Primary 1 Delayed Write Upstream Secondary X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions: PI7C8150B is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. PI7C8150B detects a data parity error on the secondary bus or detects P_PERR_L asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Table 6-6. Assertion of S_PERR_L
S_PERR_L Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/x x/x x/1 x/x x/x 1/1 x/1
1 (de-asserted) Read Downstream Primary 0 (asserted) Read Downstream Secondary 1 Read Upstream Primary 1 Read Upstream Secondary 1 Posted Write Downstream Primary 1 Posted Write Downstream Secondary 1 Posted Write Upstream Primary 0 Posted Write Upstream Secondary 1 Delayed Write Downstream Primary 1 Delayed Write Downstream Secondary 02 Delayed Write Upstream Primary 0 Delayed Write Upstream Secondary X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions: PI7C8150B has detected P_PERR_L asserted on an upstream posted write transaction or S_PERR_L asserted on a downstream posted write transaction.
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PI7C8150B did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. The SERR_L enable bit must be set in the command register. Table 6-7. Assertion of P_SERR_L for Data Parity Errors
P_SERR_L Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits x/x x/x x/x x/x x/x 1/1 1/1 x/x x/x x/x x/x x/x
1 (de-asserted) Read Downstream Primary 1 Read Downstream Secondary 1 Read Upstream Primary 1 Read Upstream Secondary 1 Posted Write Downstream Primary 02 (asserted) Posted Write Downstream Secondary 03 Posted Write Upstream Primary 1 Posted Write Upstream Secondary 1 Delayed Write Downstream Primary 1 Delayed Write Downstream Secondary 1 Delayed Write Upstream Primary 1 Delayed Write Upstream Secondary X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
6.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8150B uses the P_SERR_L signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 6.2.3. Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the following conditions apply: For PI7C8150B to assert P_SERR_L for any reason, the SERR_L enable bit must be set in the command register. Whenever PI7C8150B asserts P_SERR_L, PI7C8150B must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150B asserts P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150B also sets the received system error bit in the secondary status register. PI7C8150B also conditionally asserts P_SERR_L for any of the following reasons: Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224 (default) attempts to deliver (224 target retries received) Page 59 of 108 APRIL 2006 - Revision 2.02
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Parity error reported on target bus during posted write transaction (see previous section) Delayed write data discarded after 224 (default) attempts to deliver (224 target retries received) Delayed read data cannot be transferred from target after 224 (default) attempts (224 target retries received) Master timeout on delayed transaction The device-specific P_SERR_L status register reports the reason for the assertion of P_SERR_L. Most of these events have additional device-specific disable bits in the P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion for specific events. The master timeout condition has a SERR_L enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.
7
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK_L signal to implement exclusive access to a target for transactions that cross PI7C8150B.
7.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C8150B. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target.
7.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B
For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: The PCI bus must be idle. The LOCK_L signal must be de-asserted. The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved.
7.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
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When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target's bus. When PI7C8150B detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C8150B samples the address, transaction type, byte enable bits, and parity, as described in Section 3.5.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. The first locked transaction must be a memory read transaction. Subsequent locked transactions can be memory read or memory write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not pre-fetched. When the locked delayed memory read request is queued, PI7C8150B does not queue any more transactions until the locked sequence is finished. PI7C8150B signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C8150B. PI7C8150B allows any transactions queued before the locked transaction to complete before initiating the locked transaction. When the locked delayed memory read request transaction moves to the head of the delayed transaction queue, PI7C8150B initiates the transaction as a locked read transaction by de-asserting LOCK_L on the target bus during the first address phase, and by asserting LOCK_L one cycle later. If LOCK_L is already asserted (used by another initiator), PI7C8150B waits to request access to the secondary bus until LOCK_L is de-asserted when the target bus is idle. Note that the existing lock on the target bus could not have crossed PI7C8150B. Otherwise, the pending queued locked transaction would not have been queued. When PI7C8150B is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C8150B transfers the read data back to the initiator, and the lock is then also established on the primary bus. For PI7C8150B to recognize and respond to the initiator, the initiator's subsequent attempts of the read transaction must use the locked transaction sequence (de-assert LOCK_L during address phase, and assert LOCK_L one cycle later). If the LOCK_L sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR_L is conditionally asserted (see Section 6.4), the read data and queued read transaction are discarded, and the LOCK_L signal is de-asserted on the target bus. Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by PI7C8150B are driven as locked transactions on the target bus. The first transaction to establish LOCK_L must be Memory Read. If the first transaction is not Memory read, the following transactions behave accordingly: Type 0 Configuration Read/Write induces master abort Type 1 Configuration Read/Write induces master abort I/O Read induces master abort I/O Write induces master abort Page 61 of 108 APRIL 2006 - Revision 2.02
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Memory Write induces master abort When PI7C8150B receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C8150B resumes forwarding unlocked transactions in both directions.
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8150B ignores upstream lock and transactions. PI7C8150B will pass these transactions as normal transactions without lock established.
7.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8150B must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. An established target lock is maintained until the initiator relinquishes the lock. PI7C8150B does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK_L signal at end of the transaction. When the last locked transaction is a delayed transaction, PI7C8150B has already completed the transaction on the target bus. In this example, as soon as PI7C8150B detects that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state while FRAME_L is de-asserted, PI7C8150B de-asserts the LOCK_L signal on the target bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until several cycles after the last locked transaction has been completed on the target bus. As soon as PI7C8150B has de-asserted LOCK_L to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. When the last locked transaction is a posted write transaction, PI7C8150B de-asserts LOCK_L on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. When PI7C8150B receives a target abort or a master abort in response to a locked delayed transaction, PI7C8150B returns a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then de-assert LOCK_L at the end of the transaction. PI7C8150B sets the appropriate status bits, flagging the abnormal target termination condition (see Section 3.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When PI7C8150B receives a target abort or a master abort in response to a locked posted write transaction, PI7C8150B cannot pass back that status to the initiator. PI7C8150B asserts SERR_L on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR_L enable bit is set in the command register.
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Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 6.4).
8
PCI BUS ARBITRATION
PI7C8150B must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C8150B, typically on the motherboard. For the secondary PCI bus, PI7C8150B implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
8.1
PRIMARY PCI BUS ARBITRATION
PI7C8150B implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L, for primary PCI bus arbitration. PI7C8150B asserts P_REQ_L when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C8150B keeps P_REQ_L asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C8150B on the primary PCI bus, PI7C8150B de-asserts P_REQ_L for two PCI clock cycles. For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter after PI7C8150B has asserted P_REQ_L, PI7C8150B initiates a transaction on the primary bus during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8150B when P_REQ_L is not asserted, PI7C8150B parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C8150B and PI7C8150B has a transaction to initiate on the primary bus, PI7C8150B starts the transaction if P_GNT_L was asserted during the previous cycle.
8.2
SECONDARY PCI BUS ARBITRATION
PI7C8150B implements an internal secondary PCI bus arbiter. This arbiter supports eight external masters on the secondary bus in addition to PI7C8150B. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration.
8.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied LOW. PI7C8150B has nine secondary bus request input pins, S_REQ_L[8:0], and has nine secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN_L is HIGH.
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Figure 8-1
Secondary Arbiter Example
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 9 requests / grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure 9-1 shows an example of an internal arbiter where four masters, including PI7C8150B, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on. Each bus master, including PI7C8150B, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbitercontrol register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group, and PI7C8150B is assigned to the high priority group. PI7C8150B receives highest priority on the target bus every other transaction and priority rotates evenly among the other masters. Priorities are re-evaluated every time S_FRAME_L is asserted at the start of each new transaction on the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now has the lowest priority in its group. If PI7C8150B detects that an initiator has failed to assert S_FRAME_L after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
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busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one grant and asserted another grant during the same PCI clock cycle.
8.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit 31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0) clocks. If the current master occupies the bus and other masters are waiting, the current master will be preempted by removing its grant (GNT#) after the next master waits for the time-to-preempt.
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN_L, is tied HIGH. An external arbiter must then be used. When S_CFN_L is tied HIGH, PI7C8150B, reconfigures two pins to be external request and grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because it's an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because it's an input. When an external arbiter is used, PI7C8150B uses the S_GNT_L[0] pin to request the secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after PI7C8150B has asserted S_GNT_L[0], PI7C8150B initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C8150B has not asserted the request, PI7C8150B parks AD, CBE and PAR pins by driving them to valid logic levels. The unused secondary bus grant outputs, S_GNT_L[8:1] are driven HIGH. The unused secondary bus request inputs, S_REQ_L[8:1], should be pulled HIGH.
8.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device's request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later. PI7C8150B parks the primary bus only when P_GNT_L is asserted, P_REQ_L is deasserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8150B 3states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8150B is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C8150B can start the transaction on the next PCI clock cycle by asserting P_FRAME_L if P_GNT_L is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C8150B keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C8150B parks the secondary bus at itself until transactions start occurring on the secondary bus. Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8150B. By default, offset 48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8150B parks Page 65 of 108 APRIL 2006 - Revision 2.02
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the secondary bus only when the reconfigured grant signal, S_REQ_L[0], is asserted and the secondary bus is idle.
9
CLOCKS
This chapter provides information about the clocks.
9.1
PRIMARY CLOCK INPUTS
PI7C8150B implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. In synchronous mode, the secondary clock is derived internally from the primary clock, P_CLK. PI7C8150B operates at a maximum frequency of 66 MHz (33MHz for PI7C8150B-33).
9.2
SECONDARY CLOCK OUTPUTS
PI7C8150B has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock inputs for up to nine external secondary bus devices. In synchronous mode, the S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: Each secondary clock output is limited to no more than one load.
9.3
ASYNCHRONOUS MODE
In asynchronous mode, the PI7C8150B can be run in the following frequency configuration: Primary (MHz) 25MHz to 66MHz Secondary (MHz) 25MHz to 66MHz
PI7C8150B-33 can be run in the following frequency configuration: Primary (MHz) 25MHz to 33MHz Secondary (MHz) 25MHz to 33MHz
To set asynchronous mode support, MS0 and MS1 must be configured accordingly: MS0 0 0 1 1 MS1 0 1 0 1 Description Reserved for future use Reserved for future use Synchronous Mode Asynchronous Mode
When MS0 and MS1 are pulled to HIGH during the deassertion of P_RST, PI7C8150B will go into asynchronous mode. The secondary clock outputs will then be derived from Page 66 of 108 APRIL 2006 - Revision 2.02
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ASYNC_CLKIN and not P_CLK. S_CLKOUT[9] is still connected to S_CLKIN to provide the same timing as the bus clocks. CFG66/SCAN_EN_H becomes CLK_RATE in asynchronous mode. Pulling CLK_RATE HIGH sets S_CLKOUT[9:0] equal to ASYNC_CLKIN. Pulling CLK_RATE LOW sets S_CLKOUT[9:0] to half the frequency of ASYNC_CLKIN. PI7C8150B will not be able to drive S_M66EN in asynchronous mode.
10
GENERAL PURPOSE I/O INTERFACE
The PI7C8150B implements a 4-pin general purpose I/O interface. During normal operation, device specific configuration registers control the GPIO interface. The GPIO interface can be used for the following functions: During secondary interface reset, the GPIO interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150B to a halt through hardware, permitting live insertion of option cards behind the PI7C8150B.
10.1
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the GPIO interface: The GPIO output data register The GPIO output enable control register The GPIO input data register These registers consist of five 8-bit fields: Write-1-to-set output data field Write-1-to-clear output data field Write-1-to-set signal output enable control field Write-1-to-clear signal output enable control field Input data field The bottom four bits of the output enable fields control whether each GPIO signal is input only or bi-directional. Each signal is controlled independently by a bit in each output enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tristated, and the pin is then input only. Writing zeroes to these registers has no effect. The reset for these signals is input only. The input data field is read only and reflects the current value of the GPIO pins. A type 0 configuration read operation to this address is used to obtain the values of these pins. All pins can be read at any time, whether configured as input only or as bi-directional. The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is written to the write-1-to-set field and the pin is enabled as an output, the corresponding GPIO output is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is Page 67 of 108 APRIL 2006 - Revision 2.02
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enabled as an output, the corresponding GPIO output is driven LOW. Writing zeros to these registers has no effect. The value written to the output register will be driven only when the GPIO signal is configured as bi-directional. A type 0 configuration write operation is used to program these fields. The rest value for the output is 0.
10.2
SECONDARY CLOCK CONTROL
The PI7C8150B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. The serial data stream is shifted in as soon as P_RST_L is detected deasserted and the secondary reset signal, S_RST_L, is detected asserted. The deassertion of S_RST_L is delayed until the PI7C8150B completes shifting in the clock mask data, which takes 23 clock cycles. After that, the GPIO pins can be used as general-purpose I/O pins. An external shift register should be used to load and shift the data. The GPIO pins are used for shift register control and serial data input. Table 10-1 shows the operation of the GPIO pins. Table 10-1. GPIO Operation
GPIO Pin GPIO[0] GPIO[1] GPIO[2] Operation Shift register clock output at 33MHz max frequency Not used Shift register control 0: Load 1: Shift Not used
GPIO[3]
The data is input through the dedicated input signal, MSK_IN. The shift register circuitry is not necessary for correct operation of PI7C8150B. The shift register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock outputs or tied HIGH to force all secondary clock outputs HIGH. Table 10-2 shows the format of the serial stream. Table 10-2. GPIO Serial Data Format
Bit [1:0] [3:2] [5:4] [7:6] [8] [9] [10] [11] [12] [13] [14] [15] Description Slot 0 PRSNT#[1:0] or device 0 Slot 1 PRSNT#[1:0] or device 1 Slot 2 PRSNT#[1:0] or device 2 Slot 3 PRSNT#[1:0] or device 3 Device 4 Device 5 Device 6 Device 7 Device 8 PI7C8150B S_CLKIN Reserved Reserved S_CLKOUT 0 1 2 3 4 5 6 7 8 9 NA NA
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that indicates that a card is present in the slot and therefore the secondary clock for that slot is Page 68 of 108 APRIL 2006 - Revision 2.02
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not masked. If these clocks are connected to devices and not to slots, one or both of the bits should be tied low to enable the clock. The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1 disables the clock. Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150B's S_CLKIN input. If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150B's S_CLKIN input can be rearranged from the assignment shown here. However, it is important that the serial data stream format match the assignment of S_CLKOUT. The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits are tied high to disable their respective secondary clocks because those clocks are not connected to anything. The next bit is tied LOW because that secondary clock output is connected to the PI7C8150B S_CLKIN input. When the secondary reset signal, S_RST_L, is detected asserted and the primary reset signal, P_RST_L, is detected deasserted, PI7C8150B drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift register. On the next cycle, PI7C8150B drives GPIO[2] HIGH to perform a shift operation. This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the least significant bit is shifted in last. After the shift operation is complete, PI7C8150B tri-states the GPIO signals and can deassert S_RST_L if the secondary reset bit is clear. PI7C8150B then ignores MSK_IN. Control of the GPIO signal now reverts to PI7C8150B GPIO control registers. The clock disable mask can be modified subsequently through a configuration write command to the secondary clock control register in device-specific configuration space.
10.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction forwarding. To enable live insertion mode, the live insertion mode bit in the chip control register must be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO output enable control register. When live insertion mode is enabled, whenever GPIO[3] is driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This means that, as a target, PI7C8150B no longer accepts any I/O or memory transactions, on either interface. When read, the register bits still reflect the value originally written by a configuration write command; when GPIO[3] is deasserted, the internal enable bits return to their original value (as they appear when read from the command register). When this mode is enabled, as a master, PI7C8150B completes any posted write or delayed request transactions that have already been queued. Delayed completion transactions are not returned to the master in this mode because PI7C8150B is not responding to any I/O or memory transactions during this time. PI7C8150B continues to accept configuration transactions in live insertion mode. Once live insertion mode brings PI7C8150B to a halt and queued transactions are completed, the secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired, to reset and tri-state secondary bus devices, and to enable any live insertion hardware.
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11
PCI POWER MANAGEMENT
PI7C8150B incorporates functionality that meets the requirements of the PCI Power Management Specification, Revision 1.0. These features include: PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism Support for D0, D3 hot and D3 cold power management states Support for D0, D1, D2, D3 hot , and D3 cold power management states for devices behind the bridge Support of the B2 secondary bus power state when in the D3 hot power management state Table 11-1 shows the states and related actions that PI7C8150B performs during power management transitions. (No other transactions are permitted.) Table 11-1. Power Management Transitions
Current Status D0 D0 D0 D0 D3hot Next State D3cold D3hot D2 D1 D0 Action Power has been removed from PI7C8150B. A power-up reset must be performed to bring PI7C8150B to D0. If enabled to do so by the BPCCE pin, PI7C8150B will disable the secondary clocks and drive them LOW. Unimplemented power state. PI7C8150B will ignore the write to the power state bits (power state remains at D0). Unimplemented power state. PI7C8150B will ignore the write to the power state bits (power state remains at D0). PI7C8150B enables secondary clock outputs and performs an internal chip reset. Signal S_RST_L will not be asserted. All registers will be returned to the reset values and buffers will be cleared. Power has been removed from PI7C8150B. A power-up reset must be performed to bring PI7C8150B to D0. Power-up reset. PI7C8150B performs the standard power-up reset functions as described in Section 12.
D3hot D3cold
D3cold D0
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C8150B has a reset input, P_RESET_L. When P_RESET_L is asserted, the following events occur: PI7C8150B immediately tri-states all primary and secondary PCI interface signals.
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PI7C8150B performs a chip reset. Registers that have default values are reset. P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT. PI7C8150B is not accessible during P_RESET_L. After P_RESET_L is deasserted, PI7C8150B remains inaccessible for 16 PCI clocks before the first configuration transaction can be accepted.
12.2
SECONDARY INTERFACE RESET
PI7C8150B is responsible for driving the secondary bus reset signals, S_RESET_L. PI7C8150B asserts S_RESET_L when any of the following conditions are met: Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted. The secondary reset bit in the bridge control register is set. Signal S_RESET_L remains asserted until a configuration write operation clears the secondary reset bit. S_RESET_L pin is asserted. When S_RESET_L is asserted, PI7C8150B immediately 3states all the secondary PCI interface signals associated with the secondary port. The S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK. When S_RESET_L is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR are driven low for the duration of S_RESET_L assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150B remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
12.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8150B and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. S_RESET_L is asserted and the secondary reset bit is automatically set. S_RESET_L remains asserted until a configuration write operation clears the secondary reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after completion of the configuration write operation, PI7C8150B's reset bit automatically clears and PI7C8150B is ready for configuration. During reset, PI7C8150B is inaccessible.
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13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0] 0000 0001 0010 Command Interrupt Acknowledge Special Cycle I/O Read Action Ignore Do not claim. Ignore. 1. If address is within pass through I/O range, claim and pass through. 2. Otherwise, do not pass through and do not claim for internal access. Same as I/O Read. --------1. If address is within pass through memory range, claim and pass through. 2. If address is within pass through memory mapped I/O range, claim and pass through. 3. Otherwise, do not pass through and do not claim for internal access. Same as Memory Read. --------Type 0 Configuration Read: If the bridge's IDSEL line is asserted, perform function decode and claim if target function is implemented. Otherwise, ignore. If claimed, permit access to target function's configuration registers. Do not pass through under any circumstances. Type 1 Configuration Read: 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Read. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through as a Type 1 Configuration Read. 3. Otherwise, ignore. Type 0 Configuration Write: same as Configuration Read. Type 1 Configuration Write (not special cycle request): 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Write 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a Type 1 Configuration Write. 3. Otherwise, ignore. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h) 1. If the target bus is the bridges secondary bus: claim and pass through as a special cycle.
0011 0100 0101 0110
I/O Write Reserved Reserved Memory Read
0111 1000 1001 1010
Memory Write Reserved Reserved Configuration Read
1011
Configuration Write
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P_CBE [3:0]
Command
Action 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 Configuration Write. 3. Otherwise ignore Same as Memory Read Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
13.2
SECONDARY INTERFACE
S_CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Action Ignore Do not claim. Ignore. Same as Primary Interface Same as I/O Read. --------Same as Primary Interface Same as Memory Read. --------Ignore I. Type 0 Configuration Write: Ignore II. Type 1 Configuration Write (not special cycle request):Ignore III. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h): 1. If the target bus is the bridge's primary bus: claim and pass through as a Special Cycle 2. If the target bus is neither the primary bus nor is it in range of buses defined by the bridge's secondary and subordinate bus registers: claim and pass through unchanged as a Type 1 Configuration Write. 3. If the target bus is not the bridge's primary bus, but is in range of buses defined by the bridge's secondary and subordinate bus registers: ignore. Same as Memory Read Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
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14
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte space (configuration header) to define various attributes of PI7C8150B as shown below.
14.1
CONFIGURATION REGISTER
31-24 Device ID Primary Status Reserved Class Code Header Type 23-16 15-8 Vendor ID Command 7-0 Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch
Bus Arbiter Preemption Control
Revision ID Primary Latency Timer Cache Line Size Reserved Reserved Secondary Latency Subordinate Bus Secondary Bus Primary Bus Number Timer Number Number Secondary Status I/O Limit I/O Base Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base Prefetchable Base Upper 32-bit Prefetchable Limit Upper 32-bit I/O Limit Upper 16-bit I/O Base Upper 16-bit Reserved Capability Pointer to DCh Reserved Bridge Control Reserved Interrupt Line Arbiter Control Diagnostic / Chip Control Reserved Upstream Memory Control Extended Chip Control Secondary Hot Swap Switch Time Slot
Upstream (S to P) Memory Limit Upstream (S to P) Memory Base Upstream (S to P) Memory Base Upper 32-bit Upstream (S to P) Memory Limit Upper 32-bit Reserved Reserved GPIO Data and Control P_SERR# Event Disable Reserved P_SERR_L Status Secondary Clock Control Reserved Reserved Reserved Port Option Retry Counter Reserved Secondary Master Timeout Counter Primary Master Timeout Counter Reserved Chassis Number Slot Number Next Pointer Capability ID Reserved Power Management Capabilities Next Item Pointer Capability ID Reserved PPB Support Extensions Power Management Data Reserved Next Pointer Capability ID Reserved
50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h-AFh B0h B4h-D8h DCh E0h E4h E8h-FFh
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14.1.1
VENDOR ID REGISTER - OFFSET 00h
Bit 15:0 Function Vendor ID Type R/O Description Identifies Pericom as vendor of this device. Hardwired as 12D8h.
14.1.2
DEVICE ID REGISTER - OFFSET 00h
Bit 31:16 Function Device ID Type R/O Description Identifies this device as the PI7C8150B. Hardwired as 8150h.
14.1.3
COMMAND REGISTER - OFFSET 04h
Bit Function Type Description Controls response to I/O access on the primary interface 0: ignore I/O transactions on the primary interface 0 I/O Space Enable R/W 1: enable response to I/O transactions on the primary interface Reset to 0 Controls response to memory accesses on the primary interface Memory Space Enable 0: ignore memory transactions on the primary interface R/W 1: enable response to memory transactions on the primary interface Reset to 0 Controls ability to operate as a bus master on the primary interface 0: do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface R/W 1: enables 7C8150 to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface Reset to 0 No special cycles defined. Bit is defined as read only and returns 0 when read Memory write and invalidate not supported. Bit is implemented as read only and returns 0 when read (unless forwarding a transaction for another master) Controls response to VGA compatible palette accesses 0: ignore VGA palette accesses on the primary 5 VGA Palette Snoop Enable R/W 1: enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded and may be any value) Controls response to parity errors 0: 7C8150 may ignore any parity errors that it detects and continue normal operation R/W 1: 7C8150 must take its normal action when a parity error is detected Reset to 0
1
2
Bus Master Enable
3 4
Special Cycle Enable Memory Write And Invalidate Enable
R/O R/O
6
Parity Error Response
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Bit
Function
Type
Description Controls the ability to perform address / data stepping 0: disable address/data stepping (affects primary and secondary)
7
Wait Cycle Control
R/O 1: enable address/data stepping (affects primary and secondary) Reset to 0 Controls the enable for the P_SERR_L pin
8
P_SERR_L enable
0: disable the P_SERR_L driver R/W 1: enable the P_SERR_L driver Reset to 0 Controls 7C8150's ability to generate fast back-to-back transactions to different devices on the primary interface.
9
Fast Back-toBack Enable
R/W
0: no fast back-to-back transactions 1: enable fast back-to-back transactions Reset to 0 Returns 000000 when read
15:10
Reserved
R/O
14.1.4
STATUS REGISTER - OFFSET 04h
Bit 19:16 20 Function Reserved Capabilities List Type R/O R/O Description Reset to 0 Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) Reset to 1 Set to 1 to enable 66MHz operation on the primary interface Reset to 1 Reset to 0 Set to 1 to enable decoding of fast back-to-back transactions on the primary interface to different targets Reset to 1 Set to 1 when P_PERR_L is asserted and bit 6 of command register is set Reset to 0 DEVSEL_L timing (medium decoding) 00: fast DEVSEL_L decoding 01: medium DEVSEL_L decoding 10: slow DEVSEL_L decoding 11: reserved Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 Set to 1 (by a master device) whenever transactions are terminated with target aborts Reset to 0 Set to 1 (by a master) when transactions are terminated with Master Abort Reset to 0
21
66MHz Capable
R/O
22 23
Reserved Fast Back-toBack Capable
R/O R/O
24
Data Parity Error Detected
R/WC
26:25
DEVSEL_L timing
R/O
27
Signaled Target Abort Received Target Abort
R/WC
28
R/WC
29
Received Master Abort
R/WC
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Bit 30
Function Signaled System Error Detected Parity Error
Type R/WC
Description Set to 1 when P_SERR_L is asserted Reset to 0 Set to 1 when address or data parity error is detected on the primary interface Reset to 0
31
R/WC
14.1.5
REVISION ID REGISTER - OFFSET 08h
Bit 7:0 Function Revision Type R/O Description Indicates revision number of device. Hardwired to 02h
14.1.6
CLASS CODE REGISTER - OFFSET 08h
Bit 15:8 23:16 31:24 Function Programming Interface Sub-Class Code Base Class Code Type R/O R/O R/O Description Read as 0 to indicate no programming interfaces have been defined for PCI-to-PCI bridges Read as 04h to indicate device is PCI-to-PCI bridge Read as 06h to indicate device is a bridge device
14.1.7
CACHE LINE SIZE REGISTER - OFFSET 0Ch
Bit 7:0 Function Cache Line Size Type R/W Description Designates the cache line size for the system and is used when terminating memory write and invalidate transactions and when prefetching memory read transactions. Only cache line sizes (in units of 4-byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). Reset to 0
14.1.8
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
Bit 15:8 Function Primary Latency timer Type R/W Description This register sets the value for the Master Latency Timer, which starts counting when the master asserts FRAME_L. Reset to 0
14.1.9
HEADER TYPE REGISTER - OFFSET 0Ch
Bit 23:16 Function Header Type Type R/O Description Read as 01h to indicate that the register layout conforms to the standard PCI-to-PCI bridge layout.
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14.1.10
PRIMARY BUS NUMBER REGISTSER - OFFSET 18h
Bit 7:0 Function Primary Bus Number Type R/W Description Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 0
14.1.11
SECONDARY BUS NUMBER REGISTER - OFFSET 18h
Bit 15:8 Function Secondary Bus Number Type R/W Description Indicates the number of the PCI bus to which the secondary interface is connected. The value is set in software during configuration. Reset to 0
14.1.12
SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h
Bit 23:16 Function Subordinate Bus Number Type R/W Description Indicates the number of the PCI bus with the highest number that is subordinate to the bridge. The value is set in software during configuration. Reset to 0
14.1.13
SECONDARY LATENCY TIMER REGISTER - OFFSET 18h
Bit 31:24 Function Secondary Latency Timer Type R/W Description Latency timer for secondary. Indicates the number of PCI clocks from the assertion of S_FRAME_L to the expiration of the timer when the Bridge is acting as a master on the secondary. 0: Bridge ends the transaction after the first data transfer when the Bridge's secondary bus grant has been deasserted, with the exception of memory write and invalidate transactions. Reset to 0
14.1.14
I/O BASE REGISTER - OFFSET 1Ch
Bit 3:0 7:4 Function 32-bit Indicator I/O Base Address [15:12] Type R/O R/W Description Read as 01h to indicate 32-bit I/O addressing Defines the bottom address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0
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14.1.15
I/O LIMIT REGISTER - OFFSET 1Ch
Bit 11:8 15:12 Function 32-bit Indicator I/O Base Address [15:12] Type R/O R/W Description Read as 01h to indicate 32-bit I/O addressing Defines the top address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0
14.1.16
SECONDARY STATUS REGISTER - OFFSET 1Ch
Bit 20:16 21 Function Reserved 66MHz Capable Type R/O R/O Description Reset to 0 Set to 1 to enable 66MHz operation on the secondary interface Reset to 1 Reset to 0 Set to 1 to enable decoding of fast back-to-back transactions on the secondary interface to different targets Reset to 0 Set to 1 when S_PERR_L is asserted and bit 6 of command register is set Reset to 0 DEVSEL# timing (medium decoding) 00: fast DEVSEL_L decoding 01: medium DEVSEL_L decoding 10: slow DEVSEL_L decoding 11: reserved Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary interface Reset to 0 Set to 1 (by a master device) whenever transactions on its secondary interface are terminated with target abort Reset to 0 Set to 1 (by a master) when transactions on its secondary interface are terminated with Master Abort Reset to 0 Set to 1 when S_SERR_L is asserted R/WC Reset to 0 Set to 1 when address or data parity error is detected on the secondary interface Reset to 0
22 23
Reserved Fast Back-toBack Capable Master Data Parity Error Detected
R/O R/O
24
R/WC
26:25
DEVSEL_L timing
R/O
27
Signaled Target Abort
R/WC
28
Received Target Abort
R/WC
29
Received Master Abort Received System Error Detected Parity Error
R/WC
30
31
R/WC
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14.1.17
MEMORY BASE REGISTER - OFFSET 20h
Bit 3:0 Function Type R/O Description Lower four bits of register are read only and return 0. Reset to 0 Defines the bottom address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 0
15:4
Memory Base Address [15:4]
R/W
14.1.18
MEMORY LIMIT REGISTER - OFFSET 20h
Bit 19:16 Function Type R/O Description Lower four bits of register are read only and return 0. Reset to 0 Defines the top address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh.
31:20
Memory Limit Address [31:20]
R/W
14.1.19
PEFETCHABLE MEMORY BASE REGISTER - OFFSET 24h
Bit 3:0 Function 64-bit addressing Type R/O Description Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 Defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
15:4
Prefetchable Memory Base Address [31:20]
R/W
14.1.20
PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h
Bit 19:16 Function 64-bit addressing Type R/O Description Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 Defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh.
31:20
Prefetchable Memory Limit Address [31:20]
R/W
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14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h
Bit 31:0 Function Prefetchable Memory Base Address, Upper 32-bits [63:32] Type R/W Description Defines the upper 32-bits of a 64-bit bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch
Bit 31:0 Function Prefetchable Memory Limit Address, Upper 32-bits [63:32] Type R/W Description Defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h
Bit 15:0 Function I/O Base Address, Upper 16-bits [31:16] Type R/W Description Defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h
Bit 31:0 Function I/O Limit Address, Upper 16-bits [31:16] Type R/W Description Defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
14.1.25
ECP POINTER REGISTER - OFFSET 34h
Bit 7:0 Function Enhanced Capabilities Port Pointer Type R/O Description Enhanced capabilities port offset pointer. Read as DCh to indicate that the first item resides at that configuration offset.
14.1.26
INTERRUPT LINE REGISTER - OFFSET 3Ch
Bit 7:0 Function Interrupt Line Type R/W Description For POST to program to FFh, indicating that the PI7C8150B does not implement an interrupt pin.
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14.1.27
INTERRUPT PIN REGISTER - OFFSET 3Ch
Bit 15:8 Function Interrupt Pin Type R/O Description Interrupt pin not supported on the PI7C8150B
14.1.28
BRIDGE CONTROL REGISTER - OFFSET 3Ch
Bit 16 Function Parity Error Response Type R/W Description Controls the bridge's response to parity errors on the secondary interface. 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporting and detection on the secondary interface Reset to 0 Controls the forwarding of S_SERR_L to the primary interface. 0: disable the forwarding of S_SERR_L to primary interface 1: enable the forwarding of S_SERR_L to primary interface Reset to 0 Modifies the bridge's response to ISA I/O addresses, applying only to those addresses falling within the I/O base and limit address registers and within the first 64KB or PCI I/O space. 0: forward all I/O addresses in the range defined by the I/O base and I/O limit registers 1: blocks forwarding of ISA I/O addresses in the range defined by the I/O base and I/O limit registers that are in the first 64KB of I/O space that address the last 768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block Reset to 0 Controls the bridge's response to VGA compatible addresses. 0: does not forward VGA compatible memory and I/O addresses from primary to secondary 1: forward VGA compatible memory and I/O addresses from primary to secondary regardless of other settings Reset to 0 Reserved. Returns 0 when read. Reset to 0 Control's bridge's behavior responding to master aborts on secondary interface. 0: does not report master aborts (returns FFFF_FFFFh on reads and discards data on writes) 1: reports master aborts by signaling target abort if possible by the assertion of P_SERR_L if enabled Reset to 0
17
S_SERR_L enable
R/W
18
ISA enable
R/W
19
VGA enable
R/W
20 21
Reserved Master Abort Mode
R/O R/W
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Bit 22
Function Secondary Interface Reset
Type R/W
Description Controls the assertion of S_RESET_L signal pin on the secondary interface 0: does not force the assertion of S_RESET_L pin 1: forces the assertion of S_RESET_L Reset to 0 Controls bridge's ability to generate fast back-to-back transactions to different devices on the secondary interface. 0: does not allow fast back-to-back transactions 1: enables fast back-to-back transactions Reset to 0 Set's the maximum number of PCI clocks the bridge will wait for an initiator on the primary to repeat a delayed transaction request. The counter starts right after the delayed transaction is at the front of the queue. If the master has not repeated at least once before the counter expires, the bridge discards the transaction from the queue. 0: 2 1: 2
15 10
23
Fast Back-toBack Enable
R/W
24
Primary Master Timeout
R/W
PCI clocks PCI clocks
25
Secondary Master Timeout
R/W
Reset to 0 Set's the maximum number of PCI clocks the bridge will wait for an initiator on the secondary to repeat a delayed transaction request. The counter starts right after the delayed transaction is at the front of the queue. If the master has not repeated at least once before the counter expires, the bridge discards the transaction from the queue. 0: 2 1: 2
15 10
PCI clocks PCI clocks
26
Master Timeout Status
R/WC
Reset to 0 This bit is set to 1 when either the primary master timeout counter or secondary master timeout counter expires. Reset to 0 This bit is set to 1 and P_SERR_L is asserted when either the primary discard timer or the secondary discard timer expire. Reset to 0 Reserved. Returns 0 when read. Reset to 0.
27
Discard Timer P_SERR_L enable Reserved
R/W
31-28
R/O
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER - OFFSET 40h
Bit 0 1 Function Reserved Memory Write Disconnect Control Type R/O R/W Description Reserved. Returns 0 when read. Reset to 0 Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary Reset to 0 Reserved. Returns 0 when read. Reset to 0.
3:2
Reserved
R/O
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Bit 4
Function Secondary Bus Prefetch Disable
Type R/W
Description Controls the bridge's ability to prefetch during upstream memory read transactions. 0: The bridge prefetches and does not forward byte enable bits during upstream memory reads. 1: The bridge requests only 1 DWORD from the target and forwards read byte enable bits during upstream memory reads. Reset to 0 Enables hardware control of transaction forwarding. 0: GPIO[3] has no effect on the I/O, memory, and master enable bits 1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask I/O enable, memory enable and master enable bits to 0. PI7C8150B will stop accepting I/O and memory transactions as a result. Reset to 0 Reserved. Returns 0 when read. Reset to 0 Controls the chip and secondary bus reset. 0: PI7C8150B is ready for operation 1: Causes PI7C8150B to perform a chip reset Controls the testability of the bridge's internal counters. The bits are used for chip test only. 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised Reset to 0 Reserved. Returns 0 when read. Reset to 0.
5
Live Insertion Mode
R/W
7:6 8
Reserved Chip Reset
R/O R/WR
10:9
Test Mode For All Counters at P and S1
R/O
15:11
Reserved
R/O
14.1.30
ARBITER CONTROL REGISTER - OFFSET 40h
Bit 24:16 Function Arbiter Control Type R/W Description Each bit controls whether a secondary bus master is assigned to the high priority group or the low priority group. Bits [24:16] correspond to request inputs S_REQ_L[8:0] respectively. Bit 24 corresponds to S_REQ_L[8] Bit 16 corresponds to S_REQ_L[0] 0: low priority 1: high priority Reset to 0 Controls whether the secondary interface of the bridge is in the high priority group or the low priority group. 0: low priority 1: high priority Reset to 1 Reserved. Returns 0 when read. Reset to 0.
25
Priority of Secondary Interface
R/W
31:26
Reserved
R/O
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14.1.31
EXTENDED CHIP CONTROL REGISTER - OFFSET 48h
Bit Function Type Description Controls ability to do memory read flow through 0: Disable flow through during a memory read transaction R/W 1: Enable flow through during a memory read transaction Reset to 0 Controls bus arbiter's park function 0: Park to last master 1 Park R/W 1: Park to bridge Reset to 0 Controls the downstream (P to S) memory read line and memory read multiple prefetching dynamic control 2 Downstream Dynamic Prefetch Control R/W 0: Enable the downstream memory read line and memory read multiple prefetching dynamic control 1: Disable the downstream memory read line and memory read multiple prefetching dynamic control Controls the upstream (S to P) memory read line and memory read multiple prefetching dynamic control 3 Upstream Dynamic Prefetch Control R/W 0: Enable the upstream memory read line and memory read multiple prefetching dynamic control 1: Disable the upstream memory read line and memory read multiple prefetching dynamic control Reserved. Returns 0 when read. Reset to 0
0
Memory Read Flow Through Enable
15:4
Reserved
R/O
14.1.32
UPSTREAM MEMORY CONTROL REGISTER - OFFSET 48h
Bit Function Type Description 0: Upstream memory is the entire range except the down stream memory channel 1: Upstream memory is confined to upstream Memory Base and Limit (See offset 50th and 54th for upstream memory range) Reset to 0 Reserved. Returns 0 when read. Reset to 0
16
Upstream (S to P) Memory Base and Limit Enable
R/W
31:17
Reserved
R/O
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14.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER - OFFSET 4Ch
Bit Function Type Description Controls the number of clock cycles after frame is asserted before preemption is enabled. 1xxx: Preemption off 0000: Preemption enabled after 0 clock cycles 0001: Preemption enabled after 1 clock cycle Secondary bus arbiter preemption contorl 0010: Preemption enabled after 2 clock cycles R/W 0011: Preemption enabled after 4 clock cycles 0100: Preemption enabled after 8 clock cycles 0101: Preemption enabled after 16 clock cycles 0110: Preemption enabled after 32 clock cycles 0111: Preemption enabled after 64 clock cycles Reset to 0000
31:28
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER - OFFSET 50h
Bit Function Type Description 0: 32 bit addressing 1: 64 bit addressing Reset to 1 Controls upstream memory base address. R/W Reset to 00000000h
3:0
64 bit addressing
R/O
15:4
Upstream Memory Base Address
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER - OFFSET 50h
Bit Function Type Description 0: 32 bit addressing 1: 64 bit addressing Reset to 1 Controls upstream memory limit address. R/W Reset to 000FFFFFh
19:16
64 bit addressing
R/O
31:20
Upstream Memory Limit Address
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14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER - OFFSET 54h
Bit 31:0 Function Upstream Memory Base Address Type R/W Reset to 0 Description Defines bits [63:32] of the upstream memory base
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER - OFFSET 58h
Bit 31:0 Function Upstream Memory Limit Address Type R/W Reset to 0 Description Defines bits [63:32] of the upstream memory limit
14.1.38
P_SERR_L EVENT DISABLE REGISTER - OFFSET 64h
Bit 0 Function Reserved Type R/O Description Reserved. Returns 0 when read. Reset to 0 Controls PI7C8150B's ability to assert P_SERR_L when it is unable to transfer any read data from the target after 224 attempts. 0: P_SERR_L is asserted if this event occurs and the SERR_L enable bit in the command register is set. 1: P_SERR_L is not assert if this event occurs. Reset to 0 Controls PI7C8150B's ability to assert P_SERR_L when it is unable to transfer delayed write data after 224 attempts. Posted Write Non-Delivery 0: P_SERR_L is asserted if this event occurs and the SERR_L enable bit in the command register is set 1: P_SERR_L is not asserted if this event occurs Reset to 0 Controls PI7C8150B's ability to assert P_SERR_L when it receives a target abort when attempting to deliver posted write data. Target Abort During Posted Write 0: P_SERR_L is asserted if this event occurs and the SERR_L enable bit in the command register is set 1: P_SERR_L is not asserted if this event occurs Reset to 0 Controls PI7C8150B's ability to assert P_SERR_L when it receives a master abort when attempting to deliver posted write data. Master Abort On Posted Write 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0
1
Posted Write Parity Error
R/W
2
R/W
3
R/W
4
R/W
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Bit
Function
Type
Description Controls PI7C8150B's ability to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. 0: P_SERR_L is asserted if this event occurs and the SERR_L enable bit in the command register is set 1: P_SERR_L is not asserted if this event occurs Reset to 0 Controls PI7C8150B's ability to assert P_SERR_L when it is unable to transfer any read data from the target after 224 attempts.
5
Delayed Write Non-Delivery
R/W
6
Delayed Read - No Data From Target
R/W
0: P_SERR_L is asserted if this event occurs and the SERR_L enable bit in the command register is set 1: P_SERR_L is not asserted if this event occurs Reset to 0 Reserved. Returns 0 when read. Reset to 0
7
Reserved
R/O
14.1.39
GPIO DATA AND CONTROL REGISTER - OFFSET 64h
Bit Function Type Description Writing 1 to any of these bits drives the corresponding bit LOW on the GPIO[3:0] bus if it is programmed as bidirectional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to GPIO pins that are programmed as input only are not driven. Writing 0 has no effect and will show last the last value written when read. Reset to 0. Writing 1 to any of these bits drives the corresponding bit HIGH on the GPIO[3:0] bus if it is programmed as bidirectional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to GPIO pins that are programmed as input only are not driven. Writing 0 has no effect and will show last the last value written when read. Reset to 0. Writing 1 to and of these bits configures the corresponding GPIO[3:0] pin as an input only. The output driver is tristated. Writing 0 to this register has no effect and will reflect the last value written when read. Reset to 0. Writing 1 to and of these bits configures the corresponding GPIO[3:0] pin as bidirectional. The output driver is enabled and drives the value set in the output data register (65h). Writing 0 to this register has no effect and will reflect the last value written when read. Reset to 0. Reserved. Returns 0 when read. Reset to 0. Reads the state of the GPIO[3:0] pins. The state is updated on the PCI clock following a change in the GPIO[3:0] pins.
11:8
GPIO Output Write-1-to-Clear
R/WC
15:12
GPIO Output Write-1-to-Set
R/WS
19:16
GPIO Output Enable Write-1to-Clear
R/WC
23:20
GPIO Output Enable Write-1to-Set Reserved GPIO Input Data Register
R/WS
27:24 31:28
R R/O
14.1.40
SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h
Bit 1:0 Function Clock 0 disable Type R/W Description If either bit is 0, then S_CLKOUT [0] is enabled. If both bits are 1, then S_CLKOUT [0] is disabled.
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Bit 3:2 5:4 7:6 8 9 10 11 12 13 15:14
Function Clock 1 disable Clock 2 disable Clock 3 disable Clock 4 disable Clock 5 disable Clock 6 disable Clock 7 disable Clock 8 disable Clock 9 disable Reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W RO
Description If either bit is 0, then S_CLKOUT [1] is enabled. If both bits are 1, then S_CLKOUT [1] is disabled. If either bit is 0, then S_CLKOUT [2] is enabled. If both bits are 1, then S_CLKOUT [2] is disabled. If either bit is 0, then S_CLKOUT [3] is enabled. If both bits are 1, then S_CLKOUT [3] is disabled. If bit is 0, then S_CLKOUT [4] is enabled. If bit is 1, then S_CLKOUT [4] is disabled and driven low. If bit is 0, then S_CLKOUT [5] is enabled. If bit is 1, then S_CLKOUT [5] is disabled and driven low. If bit is 0, then S_CLKOUT [6] is enabled. If bit is 1, then S_CLKOUT [6] is disabled and driven low. If bit is 0, then S_CLKOUT [7] is enabled. If bit is 1, then S_CLKOUT [7] is disabled and driven low. If bit is 0, then S_CLKOUT [8] is enabled. If bit is 1, then S_CLKOUT [8] is disabled and driven low. If bit is 0, then S_CLKOUT [9] is enabled. If bit is 1, then S_CLKOUT [9] is disabled and driven low. Reserved. Returns 00 when read.
14.1.41
P_SERR_L STATUS REGISTER - OFFSET 68h
Bit 16 Function Address Parity Error Type R/WC Description 1: Signal P_SERR_L was asserted because an address parity error was detected on P or S bus. Reset to 0 1: Signal P_SERR_L was asserted because a posted write data parity error was detected on the target bus. Reset to 0 1: Signal P_SERR_L was asserted because the bridge was unable to deliver post memory write data to the target after 224 attempts. Reset to 0 1: Signal P_SERR_L was asserted because the bridge received a target abort when delivering post memory write data. Reset to 0. 1: Signal P_SERR_L was asserted because the bridge received a master abort when attempting to deliver post memory write data Reset to 0. 1: Signal P_SERR_L was asserted because the bridge was unable to deliver delayed write data after 224 attempts. Reset to 0 1: Signal P_SERR_L was asserted because the bridge was unable to read any data from the target after 224 attempts. Reset to 0. 1: Signal P_SERR_L was asserted because a master did not repeat a read or write transaction before master timeout. Reset to 0.
17
Posted Write Data Parity Error
R/WC
18
Posted Write Non-delivery Target Abort during Posted Write Master Abort during Posted Write Delayed Write Non-delivery Delayed Read - No Data from Target Delayed Transaction Master Timeout
R/WC
19
R/WC
20
R/WC
21
R/WC
22
R/WC
23
R/WC
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14.1.42
PORT OPTION REGISTER - OFFSET 74h
Bit 0 Function Reserved Type R/O Description Reserved. Returns 0 when read. Reset to 0. Controls PI7C8150B's detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from the initiator on the primary interface Reset to 0 Controls PI7C8150B's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Primary MEMW Command Alias Enable 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias MEMWI to MEMW for non-posted memory write retry cycles from initiator on the primary interface Reset to 0 Controls PI7C8150B's detection mechanism for matching memory read retry cycles from the initiator on the secondary Secondary MEMR Command Alias Enable 0: exact matching for memory read retry cycles from initiator on the secondary interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from initiator on the secondary interface Reset to 0 Controls PI7C8150B's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Secondary MEMW Command Alias Enable 0: exact matching for non-posted memory write retry cycles from initiator on the secondary interface 1: alias MEMWI to MEMW for non-posted memory write retry cycles from initiator on the secondary interface Reset to 0 Reserved. Returns 0 when read. Reset to 0. Controls PI7C8150B's detection mechanism for matching non-posted memory write and invalidate cycles from the initiator on the primary interface 0: When accepting MEMWI command at the primary interface, PI7C8150B converts MEMWI to MEMW command on the secondary interface 1: Disconnects MEMWI command at aligned cache line boundaries Controls PI7C8150B's detection mechanism for matching non-posted memory write and invalidate cycles from the initiator on the secondary interface R/W 0: When accepting MEMWI command at the secondary interface, PI7C8150B converts MEMWI to MEMW command on the primary interface 1: Disconnects MEMWI command at aligned cache line boundaries
1
Primary MEMR Command Alias Enable
R/W
2
R/W
3
R/W
4
R/W
5:6
Reserved
R/O
7
Primary MEMWI Command Alias Enable
R/W
8
Secondary MEMWI Command Alias Enable
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Bit
Function
Type
Description Controls PI7C8150B's ability to enable long requests for lock cycles 0: normal lock operation
9
Enable Long Request
R/W 1: enable long request for lock cycle Reset to 0 Control's PI7C8150B's ability to enable the secondary bus to hold requests longer.
10
Enable Secondary To Hold Request Longer
R/W
0: internal secondary master will release REQ_L after FRAME_L assertion 1: internal secondary master will hold REQ_L until there is no transactions pending in FIFO or until terminated by target Reset to 1 Control's PI7C8150B's ability to hold requests longer at the Primary Port.
11
Enable Primary To Hold Request Longer
R/W
0: internal Primary master will release REQ_L after FRAME_L assertion 1: internal Primary master will hold REQ_L until there is no transactions pending in FIFO or until terminated by target Reset to 1 Reserved. Returns 0 when read. Reset to 0.
15:12
Reserved
R/O
14.1.43
RETRY COUNTER REGISTER - OFFSET 78h
Bit 31:0 Function Retry Counter Type R/W Description Holds the maximum number of attempts that PI7C8150B will try before reporting retry timeout. Retry count set at 224 PCI clocks. Default is 0100 0000h.
14.1.44
SECONDARY BUS MASTER TIMEOUT COUNTER - OFFSET 80h
Bit Function Type Description There are 2 control settings for the secondary bus master timeout counter. Bit[25] offset 3Ch can set the counter to either 210 or 215 clocks. Bit[15:0] offset 80h may control the granularity down to 1 PCI clock (from 0h to FFFFh). Both controls will over-write each other, with the last write value being used for the initial value loaded into the timeout counter. The timeout counter will start after the last data (if less than a cache line) or the first cache line data (if more than one cache line) is completed to the bridge. Once the timeout counter expires, the corresponding data in the buffer will be discarded. Reset to 8000h.
15:0
Secondary Timeout
R/W
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14.1.45
PRIMARY BUS MASTER TIMEOUT COUNTER - OFFSET 80h
Bit Function Type Description There are 2 control settings for the primary bus master timeout counter. Bit[24] offset 3Ch can set the counter to either 210 or 215 clocks. Bit[31:16] offset 80h may control the granularity down to 1 PCI clock (from 0h to FFFFh). Both controls will over-write each other, with the last write value being used for the initial value loaded into the timeout counter. The timeout counter will start after the last data (if less than a cache line) or the first cache line data (if more than one cache line) is completed to the bridge. Once the timeout counter expires, the corresponding data in the buffer will be discarded. Reset to 8000h.
31:16
Primary Timeout
R/W
14.1.46
CAPABILITY ID REGISTER - OFFSET B0h
Bit Function Type Description Capability ID for slot identification 00h: Reserved 01h: PCI Power Management (PCIPM) 02h: Accelerated Graphics Port (AGP) 03h: Vital Product Data (VPD) 7:0 Capability ID R/O 04h: Slot Identification (SI) 05h: Message Signaled Interrupts (MSI) 06h: Compact PCI Hot Swap (CHS) 07h - 255h: Reserved Reset to 04h
14.1.47
NEXT POINTER REGISTER - OFFSET B0h
Bit 15:8 Function Next Pointer Type R/O Description Reset to 0000 0000: next pointer (00h if MS0=0 and MS1=1, or MS0=1)
14.1.48
SLOT NUMBER REGISTER - OFFSET B0h
Bit 20:16 Function Expansion Slot Number First in Chassis Reserved Type R/W Reset to 0 First in chassis R/W R/O Reset to 0 Reserved. Returns 0 when read. Reset to 0. Description Determines expansion slot number
21 23:22
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14.1.49
CHASSIS NUMBER REGISTER - OFFSET B0h
Bit 31:24 Function Chassis Number Register Type R/W Reset to 0 Description Chassis number register.
14.1.50
CAPABILITY ID REGISTER - OFFSET DCh
Bit 7:0 Function Enhanced Capabilities ID Type R/O Description Read as 01h to indicate that these are power management enhanced capability registers.
14.1.51
NEXT ITEM POINTER REGISTER - OFFSET DCh
Bit 15:8 Function Next Item Pointer Type R/O Description Points to slot number register (0Bh).
14.1.52
POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET DCh
Bit 18:16 19 20 21 24:22 25 26 31:27 Function Power Management Revision PME# Clock Auxiliary Power Device Specific Initialization Reserved D1 Power State Support D2 Power State Support PME# Support Type R/O R/O R/O R/O R/O R/O R/O R/O Description Read as 001 to indicate the device is compliant to Revision 1.0 of PCI Power Management Interface Specifications. Read as 0 to indicate PI7C8150B does not support the PME# pin. Read as 0 to indicate PI7C8150B does not support the PME# pin or an auxiliary power source. Read as 0 to indicate PI7C8150B does not have device specific initialization requirements. Read as 0 Read as 0 to indicate PI7C8150B does not support the D1 power management state. Read as 0 to indicate PI7C8150B does not support the D2 power management state. Read as 0 to indicate PI7C8150B does not support the PME# pin.
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14.1.53
POWER MANAGEMENT DATA REGISTER - OFFSET E0h
Bit Function Type Description Indicates the current power state of PI7C8150B. If an unimplemented power state is written to this register, PI7C8150B completes the write transaction, ignores the write data, and does not change the value of the field. Writing a value of D0 when the previous state was D3 cause a chip reset without asserting S_RESET_L 00: D0 state 01: not implemented 10: not implemented 11: D3 state Reset to 0 Read as 0 Read as 0 as PI7C8150B does not support the PME# pin. Read as 0 as the data register is not implemented. Read as 0 as the data register is not implemented. Read as 0 as the PME# pin is not implemented.
1:0
Power State
R/W
7:2 8 12:9 14:13 15
Reserved PME# Enable Data Select Data Scale PME status
R/O R/O R/O R/O R/O
14.1.54
CAPABILITY ID REGISTER - OFFSET E4h
Bit Function Type Description 00h: Reserved. 01h: PCI Power Management (PCIPM) 02h: Accelerated Graphics Port (AGP) 03h: Vital Product Data (VPD) 7:0 Capability ID R/O 04h: Slot Identification (SI) 05h: Message Signaled Interrupts (MSI) 06h: Compact PCI Hot Swap 07h-255h: Reserved
14.1.55
NEXT POINTER REGISTER - OFFSET E4h
Bit 15:8 Function Next Pointer Type R/O Description End of pointer (00h)
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15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator Master on Primary Target Target on Primary Response PI7C8150B does not respond. It detects this situation by decoding the address as well as monitoring the P_DEVSEL_L for other fast and medium devices on the Primary Port. PI7C8150B asserts P_DEVSEL_L, terminates the cycle normally if it is able to be posted, otherwise return with a retry. It then passes the cycle to the appropriate port. When the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C8150B does not respond and the cycle will terminate as master abort. PI7C8150B does not respond. PI7C8150B asserts S_DEVSEL_L, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. It then passes the cycle to the appropriate port. When cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C8150B does not respond.
Master on Primary
Target on Secondary
Master on Primary Master on Secondary Master on Secondary
Target not on Primary nor Secondary Port Target on the same Secondary Port Target on Primary or the other Secondary Port
Master on Secondary
Target not on Primary nor the other Secondary Port
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)
MASTER ABORT
Master abort indicates that when PI7C8150B acts as a master and receives no response (i.e., no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge de-asserts FRAME_L and then de-asserts IRDY_L.
15.2.1
15.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, and S_PAR signals. Parity should be even (i. e. an even number of`1's) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the
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read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.
15.2.3
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the P_SERR_L signal by asserting P_SERR_L for one cycle and then 3-stating two cycles after the bad address. P_SERR_L can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR_L signal two cycles after the data phase and should remain asserted for one cycle when bit 6 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL_L remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort.
15.2.4
SECONDARY IDSEL MAPPING
When PI7C8150B detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S_AD[31:16] by PI7C8150B.
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C8150B for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. PI7C8150B implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST.
16.1
BOUNDARY SCAN ARCHITECTURE
Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface
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that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers and TAP controller. Figure 16-1 illustrates how these pieces fit together to form the JTAG unit.
Figure 16-1
Test Access Port Block Diagram
16.1.1
TAP PINS
The PI7C8150B's TAP pins form a serial port composed of four input connections (TMS, TCK, TRST_L and TDI) and one output connection (TDO). These pins are described in Table 16-1. The TAP pins provide access to the instruction register and the test data registers.
16.1.2
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. The instruction register is a parallel-loadable, master/slave-configured 5-bit wide, serialshift register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along with the TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate.
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The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel data (1101 binary). When a new instruction is shifted in through TDI, the value 1101(binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices. Upon activation of the TRST_L reset pin, the latched instruction asynchronously changes to the id code instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK.
16.2
BOUNDARY SCAN INSTRUCTION SET
The PI7C8150B supports three mandatory boundary-scan instructions (BYPASS, SAMPLE and EXTEST). The table shown below lists the PI7C8150B's boundary-scan instruction codes. Table 16-1. TAP Pins
Instruction Requisite EXTEST IEEE 1149.1 Required / Opcode (binary) 00000 Description EXTEST initiates testing of external circuitry, typically boardlevel interconnects and off chip circuitry. EXTEST connects the boundary-scan register between TDI and TDO. When EXTEST is selected, all output signal pin values are driven by values shifted into the boundary-scan register and may change only of the falling edge of TCK. Also, when EXTEST is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of TCK. SAMPLE performs two functions: A snapshot of the sample instruction is captured on the rising edge of TCK without interfering with normal operation. The instruction causes boundary-scan register cells associated with outputs to sample the value being driven. On the falling edge of TCK, the data held in the boundaryscan cells is transferred to the slave register cells. Typically, the slave latched data is applied to the system outputs via the EXTEST instruction. Enable internal SCAN test CLAMP instruction allows the state of the signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. The signal driven from the component pins will not change while the CLAMP instruction is selected. BYPASS instruction selects the one-bit bypass register between TDI and TDO pins. 0 (binary) is the only instruction that accesses the bypass register. While this instruction is in effect, all other test data registers have no effect on system operation. Test data registers with both test and system functionality performs their system functions when this instruction is selected.
SAMPLE IEEE 1149.1 Required
0001
INTSCAN CLAMP
00010 00100
BYPASS
11111
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16.3
TAP TEST DATA REGISTERS
The PI7C8150B contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register's most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections describe each of the test data registers.
16.4
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C8150B.
16.5
BOUNDARY-SCAN REGISTER
The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 16-1 shows the bit order of the PI7C8150B boundary-scan register. All table cells that contain "Control" select the direction of bi-directional pins or high-impedance output pins. When a "1" is loaded into the control cell, the associated pin(s) are high-impedance or selected as output. The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the PI7C8150B's pins and on-chip system logic. The VDD, GND, and JTAG pins are NOT in the boundary-scan chain. The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK. Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register by means of the TDO serial output pin at the falling edge of TCK.
16.6
TAP CONTROLLER
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls Page 99 of 108 APRIL 2006 - Revision 2.02
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PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST_L pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). Table 16-2. JTAG Boundary Register Order
Boundary-Scan Register Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name S_AD[0] S_AD[1] S_AD[2] S_AD[3] S_AD[4] S_AD[5] S_AD[6] S_AD[7] S_CBE[0] S_AD[8] S_AD[9] S_M66EN S_AD[10] S_AD[11] S_AD[12] S_AD[13] S_AD[14] S_AD[15] S_CBE[1] S_PAR S_SERR_L S_PERR_L S_LOCK_L S_STOP_L S_DEVSEL_L S_TRDY_L S_IRDY_L S_FRAME_L S_CBE[2] S_AD[16] S_AD[17] S_AD[18] S_AD[19] S_AD[20] S_AD[21] S_AD[22] S_AD[23] S_CBE[3] S_AD[24] S_AD[25] S_AD[26] S_AD[27] S_AD[28] S_AD[29] S_AD[30] S_AD[31] S_REQ_L[0] S_REQ_L[1] Pin Number 137 138 140 141 143 144 146 147 149 150 152 153 154 159 161 162 164 165 167 168 169 171 172 173 175 176 177 179 180 182 183 185 186 188 189 191 192 194 195 197 198 200 201 203 204 206 207 2 Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR OUTPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR CONTROL BIDIR BIDIR INPUT BIDIR BIDIR BIDIR CONTROL BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR CONTROL BIDIR INPUT INPUT
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Boundary-Scan Register Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
Pin Name S_REQ_L[2] S_REQ_L[3] S_REQ_L[4] S_REQ_L[5] S_REQ_L[6] S_REQ_L[7] S_REQ_L[8] S_GNT_L[0] S_GNT_L[1] S_GNT_L[2] S_GNT_L[3] S_GNT_L[4] S_GNT_L[5] S_GNT_L[6] S_GNT_L[7] S_GNT_L[8] S_CLKIN S_RESET_L S_CFN_L GPIO[3] GPIO[2] GPIO[1] GPIO[0] S_CLKOUT[0] S_CLKOUT[1] S_CLKOUT[2] S_CLKOUT[3] S_CLKOUT[4] S_CLKOUT[5] S_CLKOUT[6] S_CLKOUT[7] S_CLKOUT[8] S_CLKOUT[9] P_RESET_L BPCCE P_CLK P_GNT_L P_REQ_L P_AD[31] P_AD[30] P_AD[29] P_AD[28] P_AD[27] P_AD[26] P_AD[25] P_AD[24] P_CBE[3] P_IDSEL P_AD[23] P_AD[22] P_AD[21] P_AD[20] P_AD[19] P_AD[18] P_AD[17] P_AD[16] P_CBE[2] P_FRAME_L P_IRDY_L
Pin Number 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 21 22 23 24 25 27 28 29 30 32 33 35 36 38 39 41 42 43 44 45 46 47 49 50 55 57 58 60 61 63 64 65 67 68 70 71 73 74 76 77 79 80 82
Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT INPUT BIDIR BIDIR BIDIR BIDIR OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT OUTPUT CONTROL BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR CONTROL BIDIR BIDIR BIDIR
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Boundary-Scan Register Number 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143
Pin Name P_TRDY_L P_DEVSEL_L P_STOP_L P_LOCK_L P_PERR_L P_SERR_L P_PAR P_CBE[1] P_AD[15] P_AD[14] P_AD[13] P_AD[12] P_AD[11] P_AD[10] P_M66EN P_AD[9] P_AD[8] P_CBE[0] P_AD[7] P_AD[6] P_AD[5] P_AD[4] P_AD[3] P_AD[2] P_AD[1] P_AD[0] CFG66 MSK_IN
Pin Number 83 84 85 87 88 89 90 92 93 95 96 98 99 101 102 107 109 110 112 113 115 116 118 119 121 122 125 126
Type BIDIR BIDIR BIDIR CONTROL INPUT BIDIR OUTPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR CONTROL INPUT INPUT
17
17.1
ELECTRICAL AND TIMING SPECIFICATIONS
MAXIMUM RATINGS
(Above which the useful life may be impaired. For user guidelines, not tested).
Storage Temperature Ambient Temperature with Power Applied - PI7C8150B Ambient Temperature with Power Applied - PI7C8150BI Supply Voltage to Ground Potentials (AVCC and VDD only) Voltage at Input Pins -65C to 150C 0C to 85C -40C to 85C -0.3V to 3.6V -0.5V to 5.5V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
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17.2
DC SPECIFICATIONS
Symbol VDD, AVCC Vih Vil Vih Vil Vipu Iil Voh Vol Voh Vol Cin CCLK CIDSEL Lpin Parameter Supply Voltage Input HIGH Voltage Input LOW Voltage CMOS Input HIGH Voltage CMOS Input LOW Voltage Input Pull-up Voltage Input Leakage Current Output HIGH Voltage Output LOW Voltage CMOS Output HIGH Voltage CMOS Output LOW Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Condition Min. 3 0.5 VDD -0.5 0.7 VDD -0.5 0.7 VDD 0 < Vin < VDD Iout = -500A Iout = 1500A Iout = -500A Iout = 1500A 0.9VDD 0.1 VDD VDD - 0.5 0.5 10 12 8 20 Max. 3.6 VDD + 0.5 0.3 VDD VDD + 0.5 0.3 VDD 10 Units V V V V V V A V V V V pF pF pF nH Notes
5
3, 4 3, 4 1, 4 1, 4 3 3 3 3 2 2 3 3 3 3
Notes: 1. CMOS Input pins: S_CFN_L, TCK, TMS, TDI, TRST_L, SCAN_EN, SCAN_TM_L 2. CMOS Output pin: TDO 3. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_DEVSEL_L, P_STOP_L, P_LOCK_L, PIDSEL_L, P_PERR_L, P_SERR_L, P_REQ_L, P_GNT_L, P_RESET_L, S_AD[31:0], S_CBE[3:0], S_PAR, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_DEVSEL_L, S_STOP_L, S_LOCK_L, S_PERR_L, S_SERR_L, S_REQ[7:0]_L, S_GNT[7:0]_L, S_RESET_L, S_EN, HSLED, HS_SW_L, HS_EN, ENUM_L. 4. VDD is in reference to the VDD of the input device.
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17.3
AC SPECIFICATIONS
Figure 17-1
PCI Signal Timing Measurement Conditions
66 MHz Min. Max. 3 5 0 2 6 2 6 2 14 33 MHz Min. Max. 7 10, 124 0 2 11 2 12 2 28
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff
Parameter Input setup time to CLK - bused signals 1,2,3 Input setup time to CLK - point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay - bused signals 1,2,3 CLK to signal valid delay - point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2
Units
ns
1. See Figure 17-1 PCI Signal Timing Measurement Conditions. 2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to S_CLKOUT. 3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0], HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR, P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L, P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD, S_CBE_L, S_PAR, S_PERR_L, S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_LOCK_L, S_DEVSEL_L, and S_STOP_L. 4. REQ_L signals have a setup of 12 and GNT_L signals have a setup of 10.
17.4
66MHZ TIMING
Symbol TSKEW TDELAY TCYCLE THIGH TLOW Parameter SKEW among S_CLKOUT[9:0] DELAY between PCLK and S_CLKOUT[9:0] P_CLK, S_CLKOUT[9:0] cycle time P_CLK, S_CLKOUT[9:0] HIGH time P_CLK, S_CLKOUT[9:0] LOW time Condition 20pF load Min. 0 3.14 15 6 6 Max. 0.250 5.07 30 Units
ns
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17.5
33MHZ TIMING
Symbol TSKEW TDELAY TCYCLE THIGH TLOW Parameter SKEW among S_CLKOUT[9:0] DELAY between PCLK and S_CLKOUT[9:0] P_CLK, S_CLKOUT[9:0] cycle time P_CLK, S_CLKOUT[9:0] HIGH time P_CLK, S_CLKOUT[9:0] LOW time Condition 20pF load Min. 0 3.14 30 11 11 Max. 0.250 5.07 Units
ns
17.6
POWER CONSUMPTION
Parameter Power Consumption at 66MHz Supply Current, ICC Typical 1.68 510 Units W mA
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18
18.1
PACKAGE INFORMATION
208-PIN FQFP PACKAGE DIAGRAM
Figure 18-1
208-pin FQFP Package Outline
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18.2
256-BALL PBGA PACKAGE DIAGRAM
Figure 18-2
256-pin PBGA Package Outline
Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php
18.3
PART NUMBER ORDERING INFORMATION
Part Number PI7C8150BMA PI7C8150BND PI7C8150BMA-33 PI7C8150BND-33 PI7C8150BMAE PI7C8150BNDE PI7C8150BMAI PI7C8150BNDI PI7C8150BMAI-33 PI7C8150BNDI-33 PI7C8150BMAIE PI7C8150BNDIE Speed 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz Pin - Package 208 - FQFP 256 - PBGA 208 - FQFP 256 - PBGA 208 - FQFP (Pb-free & Green) 256 - PBGA (Pb-free & Green) 208 - FQFP 256 - PBGA 208 - FQFP 256 - PBGA 208 - FQFP (Pb-free & Green) 256 - PBGA (Pb-free & Green) Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
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PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
NOTES:
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